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- This patch update the original google/fatcat support added
with Meteor Lake support as a workaround.
- Add initial support to build google/fatcat for Panther Lake SOC
- Add soc acpi file entry in mainboard dsdt.asl
BUG=b:348678529
TEST=Build google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar table support for fatcat. Bit 4-5 in CBI/FW_CONFIG
is used to select different sar table (index 0 to 3).
BUG=b:348678529
TEST=emerge-fatcat coreboot chromeos-bootimage
Change-Id: I2d82f76d7c11378ee5c221a6b9621b4cba83720d
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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BUG=b:348678529
TEST=Able to build google/fatcat.
Change-Id: I5c90aac4873dcc57e65e641656dca3a96f84d6b8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84543
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We use ALC256 as HDA codec on fatcat hence, added the verb table.
BUG=b:348678529
TEST=Tested audio playback using HDA ALC256 codec on PTL reference
board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d55
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84409
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:348678529
TEST=Memory training is successful on google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d51
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84406
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This commit updates the fatcat mainboard to use the Panther Lake SoC
instead of Meteor Lake.
The changes include:
- Selecting the `SOC_INTEL_PANTHERLAKE_U_H` config option.
- Updating the `mainboard_update_soc_chip_config()` function to use the
`soc_intel_pantherlake_config` struct.
- Updating the devicetree to use the `soc/intel/pantherlake` chip.
- Updating variant header files to reflect the SoC change.
This update enables support for the Panther Lake SoC and its
features on the fatcat mainboard.
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84537
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This commit removes the virtual GPIOs for recovery and write protection
from the fatcat variant.
These GPIOs are not utilized on the fatcat platform, and their removal
simplifies the GPIO configuration and improves code readability.
The `CROS_GPIO_DEVICE_NAME` macro is no longer applicable for Panther
Lake SoCs. Future changes will introduce a suitable GPIO device name
that meets the requirements of Panther Lake.
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I492fec28637edb2f84e9290b28dabce3f23aa867
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84536
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the fatcat flash map layout to accommodate the growth
in Panther Lake IFWI blobs over Meteor Lake.
Release FMD:
SI_ALL: 8MB -> 9MB
SI_BIOS: 24MB -> 23MB
RW_UNUSED: 4MB -> 3MB
Debug FMD:
SI_ALL: 8MB -> 9MB
SI_BIOS: 24MB -> 23MB
RW_UNUSED: 3MB -> 2MB
TEST=Able to build google/fatcat inside chroot.
Change-Id: I8febb4df5d3b3eb07ebff8e56a1ce2dfd2f52e7d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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This change adds support for soldered-down memory on the Fatcat board.
It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes
the necessary Makefiles adjustments to handle SPD data in CBFS when
this option is enabled.
* A new Kconfig option `MEMORY_SOLDERDOWN` is added to control
soldered-down memory support.
* When `MEMORY_SOLDERDOWN` is enabled, it selects:
* `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled
* `HAVE_SPD_IN_CBFS`
* The Makefile is updated to include the `variants/$(VARIANT_DIR)/
memory` subdirectory and conditionally include the `spd` subdirectory
based on `CONFIG_HAVE_SPD_IN_CBFS`.
BUG=b:348678071
TEST=Able to build google/fatcat with N-1 silicon.
Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Add the support LP5 RAM parts for fatcat:
DRAM Part Name ID to assign
H58G56BK7BX068 0 (0000)
BUG=b:347669091
TEST=emerge-fatcat coreboot
Change-Id: Idcdbbcd42dc6b1c8b13a89b1ace5b2973dde6d2b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83824
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
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This patch adds initial code block required to build google/fatcat
board with Intel Meteor Lake Silicon. Later after the initial board
power-on is successful, we shall switch to Panther Lake silicon to
build the google/fatcat reference design.
BUG=b:347669091
TEST=Able to build the google/fatcat and able to hit power-on reset
using Intel Meteor Lake SoC platform.
Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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