coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2024-08-09	mb/google/fatcat: Generate LP5 RAM ID for `H58G56BK7BX068`	Subrata Banik
	Add the support LP5 RAM parts for fatcat: DRAM Part Name ID to assign H58G56BK7BX068 0 (0000) BUG=b:347669091 TEST=emerge-fatcat coreboot Change-Id: Idcdbbcd42dc6b1c8b13a89b1ace5b2973dde6d2b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83824 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2024-06-26	mb/google/fatcat: Add minimal code support for fatcat	Subrata Banik
	This patch adds initial code block required to build google/fatcat board with Intel Meteor Lake Silicon. Later after the initial board power-on is successful, we shall switch to Panther Lake silicon to build the google/fatcat reference design. BUG=b:347669091 TEST=Able to build the google/fatcat and able to hit power-on reset using Intel Meteor Lake SoC platform. Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>