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2024-08-09mb/google/fatcat: Add support for soldered-down memorySubrata Banik
This change adds support for soldered-down memory on the Fatcat board. It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes the necessary Makefiles adjustments to handle SPD data in CBFS when this option is enabled. * A new Kconfig option `MEMORY_SOLDERDOWN` is added to control soldered-down memory support. * When `MEMORY_SOLDERDOWN` is enabled, it selects: * `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled * `HAVE_SPD_IN_CBFS` * The Makefile is updated to include the `variants/$(VARIANT_DIR)/ memory` subdirectory and conditionally include the `spd` subdirectory based on `CONFIG_HAVE_SPD_IN_CBFS`. BUG=b:348678071 TEST=Able to build google/fatcat with N-1 silicon. Change-Id: I7edc1134630940812186118a29cbbd550f0e3634 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-06-26mb/google/fatcat: Add minimal code support for fatcatSubrata Banik
This patch adds initial code block required to build google/fatcat board with Intel Meteor Lake Silicon. Later after the initial board power-on is successful, we shall switch to Panther Lake silicon to build the google/fatcat reference design. BUG=b:347669091 TEST=Able to build the google/fatcat and able to hit power-on reset using Intel Meteor Lake SoC platform. Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>