coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2024-10-07	mb/google/fatcat: Add fatcatnuvo and fatcatite variants	Pranava Y N
	This patch adds "fatcatnuvo" and "fatcatite" boards to the fatcat Kconfig. BUG=b:369728249 TEST=Able to build fatcat/fatcatnuvo/fatcatite and verify the correct configs selected in coreboot.config Change-Id: Ice3f1d711426cb356c399de6390fef6f0e6bc748 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84648 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03	mb/google/fatcat: Add Panther Lake SOC support	Saurabh Mishra
	- This patch update the original google/fatcat support added with Meteor Lake support as a workaround. - Add initial support to build google/fatcat for Panther Lake SOC - Add soc acpi file entry in mainboard dsdt.asl BUG=b:348678529 TEST=Build google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-27	mb/google/fatcat/var/fatcat: add support for wifi sar table	YH Lin
	Add wifi sar table support for fatcat. Bit 4-5 in CBI/FW_CONFIG is used to select different sar table (index 0 to 3). BUG=b:348678529 TEST=emerge-fatcat coreboot chromeos-bootimage Change-Id: I2d82f76d7c11378ee5c221a6b9621b4cba83720d Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-09-27	mb/google/fatcat/var/fatcat: Add initial FW_CONFIG	Subrata Banik
	BUG=b:348678529 TEST=Able to build google/fatcat. Change-Id: I5c90aac4873dcc57e65e641656dca3a96f84d6b8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84543 Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25	mb/google/fatcat: Add HDA verb tables	Jeremy Compostella
	We use ALC256 as HDA codec on fatcat hence, added the verb table. BUG=b:348678529 TEST=Tested audio playback using HDA ALC256 codec on PTL reference board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d55 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84409 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25	mainboard/google/fatcat: Update SoC to Panther Lake	Subrata Banik
	This commit updates the fatcat mainboard to use the Panther Lake SoC instead of Meteor Lake. The changes include: - Selecting the `SOC_INTEL_PANTHERLAKE_U_H` config option. - Updating the `mainboard_update_soc_chip_config()` function to use the `soc_intel_pantherlake_config` struct. - Updating the devicetree to use the `soc/intel/pantherlake` chip. - Updating variant header files to reflect the SoC change. This update enables support for the Panther Lake SoC and its features on the fatcat mainboard. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84537 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09	mb/google/fatcat: Add support for soldered-down memory	Subrata Banik
	This change adds support for soldered-down memory on the Fatcat board. It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes the necessary Makefiles adjustments to handle SPD data in CBFS when this option is enabled. * A new Kconfig option `MEMORY_SOLDERDOWN` is added to control soldered-down memory support. * When `MEMORY_SOLDERDOWN` is enabled, it selects: * `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled * `HAVE_SPD_IN_CBFS` * The Makefile is updated to include the `variants/$(VARIANT_DIR)/ memory` subdirectory and conditionally include the `spd` subdirectory based on `CONFIG_HAVE_SPD_IN_CBFS`. BUG=b:348678071 TEST=Able to build google/fatcat with N-1 silicon. Change-Id: I7edc1134630940812186118a29cbbd550f0e3634 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-06-26	mb/google/fatcat: Add minimal code support for fatcat	Subrata Banik
	This patch adds initial code block required to build google/fatcat board with Intel Meteor Lake Silicon. Later after the initial board power-on is successful, we shall switch to Panther Lake silicon to build the google/fatcat reference design. BUG=b:347669091 TEST=Able to build the google/fatcat and able to hit power-on reset using Intel Meteor Lake SoC platform. Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>