coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
	As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA[, ]02110-1301[, ]USA:Foundation, Inc.:" {} + $ find -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]Suite 330, Boston, MA 02111-1307[, ]USA:Foundation, Inc.:" {} + $ find -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \.patch \ -a \! -name \_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-12	Haswell: Lower TJ_MAX to 100C. Adjust critical temps to match.	ChromeOS Developer
	Change-Id: I3326b6e3c412b6360af37030cefd13d95b704e70 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1978b0f91b2e91d2251721c7c6981d51a6930b61) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6615 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21	falco: Enable EC controlled throttling	Duncan Laurie
	When the EC requests the host to throttle (for charging or thermal related reasons) the package power consumption will be limited. Right now this is set at 12W but that is somewhat arbitrary and may need tuning. 1) define the THRT method in \_TZ scope for EC to call 2) enable SCI events for throttle start and stop 3) define the power limit at 12W and set it in NVS 1) Enable CONFIG_ACPI_DEBUG=y in the kernel 2) Enable the Debug object event in acpi module acpi.debug_layer=0x7f acpi.debug_level=0x2f 3) Using EC console generate host event for throttle start > hostevent set 0x20000 4) Check dmesg for throttle start events ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q12] (Node ffff8801002c5988) [ACPI Debug] String [0x12] "EC: THROTTLE START" [ACPI Debug] String [0x10] "Enable PL1 Limit" 5) Using EC console generate host event for throttle stop > hostevent set 0x40000 6) Check dmesg for throttle stop events ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q13] (Node ffff8801002c59b0) [ACPI Debug] String [0x11] "EC: THROTTLE STOP" [ACPI Debug] String [0x11] "Disable PL1 Limit" Change-Id: I39b53a5e8abc2892846bcd214a333fe204c6da9b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63989 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4416 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21	haswell boards: Use PECI temp sensor id 0	Duncan Laurie
	The EC temperature sensors were renumbered and now PECI is at index 0. 1) boot on falco 2) check /sys/class/thermal/thermal_zone0/temp 3) check 'temps' on ec console Change-Id: Idde1457c42c80850b5b8ac22781060ed9b224d13 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61896 Reviewed-on: http://review.coreboot.org/4367 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-12	falco: Remove thermal thresholds that use CTDP	Duncan Laurie
	This CPU does not support Configurable TDP and so far does not need to use Controllable TDP. Change-Id: I15599cd4e6890dd5c9d9f99bc4e95307a8dcc827 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60657 Reviewed-on: http://review.coreboot.org/4347 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25	falco: Initial mainboard commit	Duncan Laurie
	- Only the first two DIMM SPDs are specified so far - GPIO map is updated - iSSD power sequencing removed - USB port map updated Change-Id: I4172460d3b075bfd5bb22013a6225cf0e8f95b9c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56329 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4184 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>