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path: root/src/mainboard/google/falco/devicetree.cb
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2015-05-28igd.asl rewriteVladimir Serbinenko
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-04-30cpu/intel/haswell: remove dependency on socket_rpga989Matt DeVillier
Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from Sandy Bridge/Ivy Bridge and older coreboot conventions where features were structured around socket types. Add CPU-specific options to Kconfig and required subdirs to Makefile.inc which are curently included with socket_rpga989. TEST=successfully built and booted on google/panther Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10037 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2014-08-08falco: Remove RTD2132 chip and setup from devicetreeDuncan Laurie
This disables the spread spectrum clock and avoids errata. Old-Change-Id: I04eb767f1587bb64a215a92b66cd05e099d29964 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66673 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a7bf0d818c431221f4d014e3a0130bec8db7406e) falco: Remove RTD2132 driver from kconfig Original-Change-Id: I89ad9fbfbc58878602ed85ada918524426b5bc77 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66946 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1d732eb5e4743546b8ed50c8c44965a687f61ab2) Conflicts: src/mainboard/google/falco/Kconfig Old-Change-Id: I317a0741779e272ad72b7272ef6f4a67abd66698 Reviewed-on: https://chromium-review.googlesource.com/167311 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit ffa6c89fbac04b4b6fceafd4ba97d39a285c4aa3) Squashed two commits and corrected the subject line from 2312 to 2132. Change-Id: If4f1e59999b70efe2de45522ba78051d9ed88dd7 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6527 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-21falco: Force enable ASPM on PCIe Root Port 1Duncan Laurie
Boot on falco and look in /sys/firmware/log for the string "PCIe Root Port 1 ASPM is enabled" Change-Id: Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4454 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Disable unused clocksDuncan Laurie
CLKOUT for PCIE ports 1-5 and CLKOUT_XDP are not used and can be disabled. I couldn't test this directly without a scope so instead I used a modified commit that also disabled PCIe Port 0 and saw that that correctly disabled the WLAN port. Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4451 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: add rtd2132 settings to device treeAaron Durbin
Now that the rtd2132 device has the full settings the panel timings need to be implemented. Sadly, the Tx timings in the rtd2132 aren't 1:1 with the panel's Tx timings. Below is the table equivalent: RTD2132 | Falco Panel --------+------------ T1 | T2 --------+------------ T2 | T8+T10+T12 --------+------------ T3 | T14 --------+------------ T4 | T15 --------+------------ T5 | T9+T11+T13 --------+------------ T6 | T3 --------+------------ T7 | T4 --------+------------ Change-Id: I10a3ad475d6b9485a707eb49e31afd197fc8d24d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65858 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4472 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: update ACPI C-state settingsDuncan Laurie
Since these boards do not support C10 we should not bother advertising that state in the ACPI _CST. Instead use this map: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C3) ACPI(C3) = MWAIT(C7S) Change-Id: I37eb02bf9555c74e957316a1ba9778eb2b6ee128 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62898 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Enable RTD2132 spread spectrum at 1.0%Duncan Laurie
This may need further tuning but will start at 1.0%. boot on falco and check /sys/firmware/log localhost ~ # grep RTD2132 /sys/firmware/log RTD2132: Enable 1.0% Spread Spectrum I2C: 01:35 (Realtek RTD2132 LVDS Bridge) Change-Id: I96e1c14dbc6a7bfaf1c8deb1806c48bf2fd3e32a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61895 Reviewed-on: http://review.coreboot.org/4366 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-12HDA: Enable Mini-HDA and fix up PCH-HDA initDuncan Laurie
The SystemAgent contains a mini-hd audio controller at PCI 0:3.0 which uses the same verb table init sequence as the southbridge. In order to avoid two copies of the verb table loading code I separated out the HDA verb table functions into a file that can be re-used and then added a minihd driver to the haswell northbridge. The minihd verb table is the same across devices so it can live within the minihd driver rather than needing to be specified in each separate mainboard. I also fixed up the driver for lynxpoint HDA by following the reference code. Without HDMI cable plugged in driver does not find any codec, and it does not seem to re-probe when HDMI is connected. We may be missing kernel patches for this. hda-intel 0000:00:03.0: no codecs found! With a basic kernel patch to add 0x0a0c device ID to HDA driver and with HDMI cable connected it is much happier: snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X input: HDA Intel MID HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input9 snd_hda_intel 0000:00:1b.0: irq 61 for MSI/MSI-X input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10 input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11 Change-Id: Ifa587984be4fc2801704a0368b9cdf8379c2450e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4318 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02falco: Update panel power sequence timingsDuncan Laurie
These are based on the datasheet and I included the timing values I used from the docs. Change-Id: Ib75b2c5e50ac09d1e4cf9dd22229bb0f0a8965a4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58540 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4234 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25falco: Add panel power sequence timingsDuncan Laurie
These are placeholder values until we can configure for the exact panel. Change-Id: If40367c0e5f80d46d085c89b0edae60f1ccacdaf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56808 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4197 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25falco: Initial mainboard commitDuncan Laurie
- Only the first two DIMM SPDs are specified so far - GPIO map is updated - iSSD power sequencing removed - USB port map updated Change-Id: I4172460d3b075bfd5bb22013a6225cf0e8f95b9c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56329 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4184 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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