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path: root/src/mainboard/google/drallion
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2019-09-19mb/google/drallion: add sku id base on sensor detectionEric Lai
Implementing logic base on sensor detection to determine SKU id. BUG=b:140472369 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5e71ae6b97378b78055735bbf4b6b55ffe38b978 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35366 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19mb/google/drallion: Add memory init setup for drallionThejaswani Putta
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-18mb/google/drallion: Add SPD files for drallionAmanda Huang
This change adds SPD files for Drallion. Use spd_index matrix to correspond mem_id. This can save the dummy spd index to reduce the size of SPD.bin. BUG=b:139397313 TEST=Compile successfully Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35346 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18mb/google/drallion: Enable 360 sensor detectionBernardo Perez Priego
Implementing logic to detect SKU model and enable ISH accordignly. BUG=b:140748790 Change-Id: I22fafb43dce6545851883be556a02d65a01fc386 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35303 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18mb/google/drallion: Update gpio config for drallionVarun Joshi
Source: Pin Schematics BUG=b:139370304 Signed-off-by: Varun Joshi <varun.joshi@intel.com> Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35175 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13mb/google/drallion: Use arcada_ish.bin for arcada_cmlSelma BENSAID
drallion_ish.bin is updated for drallion GPIO changes and not compatible with arcada_cml. TEST=Build and boot arcada_cml Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-12mb/google/drallion: Update memory mapIvy Jian
This will increase ME region size and reduce the BIOS region size. BUG=b:140665483 TEST='compile successfully' Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usageSubrata Banik
PchPwrOptEnable FSP UPD is for internal testing and not really available in externally released FSP source hence assigning this UPD using devicetree config dmipwroptimize doesn't do anything. TEST=Build and boot sarien/arcada. Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-11mb/google/drallion: enable Elan and Melfas touch panelEric Lai
Drallion uses the same touch panel as Sarien. Copy the deivce from Sarien. BUG=b:140415892,b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35305 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09mb/google/drallion: modify USB settingEric Lai
Based on HW schematic to modify USB setting. Drallion has two type C on left and two type A on right. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-05mb/google/drallion: modify PCIE settingEric Lai
Based on HW schematic to modify PCIE setting. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-02mb/google/drallion: add memory sku idEric Lai
Drallion will use soldered down memory and use GPP_F12 to GPP_F16 indicates mem_id. BUG=b:139397313 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a Reviewed-on: https://review.coreboot.org/c/coreboot/+/35133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-02mb/google/drallion: Enable HDA for drallion platformAamir Bohra
Enable PchHdaIDispCodecDisconnect and PchHdaAudioLinkHda for drallion variants. This is needed with FSP 1263. Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: I13d3dd832c6fbdc2aad5ba578695edb8470806e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-30mb/google/drallion: change servo board debug to UART 0Eric Lai
Drallion will change debug port UART from 2 to 0. Followed HW schematic to modify it. BUG=b:139095062 BRANCH=N/A TEST=Build without error Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-29mb/google/drallion: Update memory mapBernardo Perez Priego
This will enable to optionally inject ISH binaries into coreboot. BUG:b:139820063 TEST='compile successfully' Change-Id: I38659460726a3f647cda3bc3efd442f18aea24f0 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-29mb/google/drallion: Correct drallion HWID and add HWID for variantsMathew King
The current HWID for drallion is reported as invalid by chrome, generate new valid HWID with the following command and taking last 4 digits. `printf "%d\n" 0x$(crc32 <(echo -n '$1'))` BUG=b:140013681 Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-28mb/google/drallion: remove GBE fileEric Lai
Drallion doesn't have on board LAN, remove GBE bin file config. BUG=b:139906731 TEST=emerge-drallion coreboot chromeos-bootimage and check image-drallion.bin not include GBE region Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-28mb/google/drallion: add dummy SPD fileEric Lai
Drallion will use soldered down memory. Add dummy spd file. BUG=b:139397313 BRANCH=N/A TEST=Build and check cbfs has the dummy spd.bin Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23mb/google/drallion: Add two variants - arcada_cml & sarien_cmlThejaswani Putta
These variants are to support the sarien and arcada boards with CML SOC, the drallion variant will be used to support the upcoming drallion board. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I766bdccb6f8b6924d6ae1abbe57035f4ff1f6f17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-15mainboard/google: Fix indirect includesKyösti Mälkki
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09google/drallion: Fix build issue due to recent mergeKyösti Mälkki
One case slipped past the review and rebase of 733c28fa42 (soc/intel/{cnl,icl}: Use new power-failure-state API). Change-Id: Id01df30d10e202e9672bf5be799a84f4f202fe24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34812 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05mb/google/drallion: Add new mainboardThejaswani Putta
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake. BUG=b:138098572 Test=compiles Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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