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2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-15soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC KconfigMichael Niewöhner
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to 512 in the SoC Kconfig and drop it from the mainboard Kconfigs. Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-01-31mb/**/Kconfig: Properly override `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`. Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99 Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-28IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS
IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code and issue a message when the build is complete. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-10src/mainboard/google: Remove unused <acpi/acpi.h>Elyes HAOUAS
Change-Id: I67fc65c5e01bb134e2e3068dc6da03de1183f785 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-01mb/google/deltaur: Select board-specific options per boardFelix Singer
Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I71f22100fe56a8b88321d220f98ac03887ce6bd7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-01-01mb/google/deltaur: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I9b523ebee2d2af8585736588306ca687dfe16003 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/deltaur/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I36a02f8d509ef39983b4162188abc0cbc3d570cf Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-12mainboard: Drop `SataMode` setting from Tiger Lake devicetreesFelix Singer
All Tiger Lake mainboards use the default value for the setting `SataMode`. Thus, drop it from their devicetree. Change-Id: I291048250bc82552fde7c71a1dcda4894a61d465 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59890 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer
`SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-12google/deltaur,drallion,sarien: Refactor ChromeOS GPIOsKyösti Mälkki
Low-level GPIOs should not depend on late cros_gpios that should be guarded with CHROMEOS and implemented for the purpose of ACPI \OIPG package generation. Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-16mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cbMAULIK V VAGHELA
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `OVERRIDE_DEVICETREE` onceAngel Pons
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10soc/intel/tigerlake: Move MAX_CPUS to KconfigAndy Pont
Most of the Kconfig files for Intel SOC devices define the MAX_CPUS value within src/soc/intel/*/Kconfig. Move the definition there for Tiger Lake and remove from the mainboard Kconfig files. Signed-off-by: Andy Pont <andy.pont@sdcsystems.com> Change-Id: If145b9eb5d99821f4ce513118e4417d05f821ef5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-27vboot: update GBB flags to use altfw terminologyJoel Kitching
As per CL:2641346, update GBB flag names: GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW BUG=b:179458327 TEST=make clean && make test-abuild BRANCH=none Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04mainboards: Remove default CHROMEOS=yKyösti Mälkki
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested with CHROMEOS=n. Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-04vc/google/chromeos: Drop <acpi/vpd.asl>Kyösti Mälkki
This was used as a means to read the MAC address and dynamically return it to the ethernet driver via ACPI. The kernel team ended up going another direction so this became obsolete. Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Move include for <vc/google/chromeos.asl>Kyösti Mälkki
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driverFurquan Shaikh
This change uses the newly added meminit block driver and updates TGL SoC and mainboard code accordingly. TEST=Verified that UPDs are configured correctly with and without this change. Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-24arch/x86: Use wildcard for mb/smihandler.cKyösti Mälkki
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/google/deltaur: Restrict RW_DIAG to lower 16MiBFurquan Shaikh
This change restricts RW_DIAG region to lower 16MiB to ensure that the extended BIOS checker for FMAP does not complain about 16MiB boundary crossing. I haven't updated any other regions to occupy the newly freed space but it is fine since this board is dead and should be dropped from coreboot soon. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPDMichael Niewöhner
Replace the two obsolete LPID implementations with the new PEPD device. The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.) There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 UUID on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too. Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen
Currently the decision of whether or not to use mrc_cache in recovery mode is made within the individual platforms' drivers (ie: fsp2.0, fsp1.1, etc.). As this is not platform specific, but uses common vboot infrastructure, the code can be unified and moved into mrc_cache. The conditions are as follows: 1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain switch is true) 2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this means that memory training will occur after verified boot, meaning that mrc_cache will be filled with data from executing RW code. So in this case, we never want to use the training data in the mrc_cache for recovery mode. 3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens before verfied boot, meaning that the mrc_cache data is generated by RO code, so it is safe to use for a recovery boot. 4. Any platform that does not use vboot should be unaffected. Additionally, we have removed the MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the mrc_cache driver takes care of invalidating the mrc_cache data for normal mode. If the platform: 1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data 2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set BUG=b:150502246 BRANCH=None TEST=1. run dut-control power_state:rec_force_mrc twice on lazor ensure that memory retraining happens both times run dut-control power_state:rec twice on lazor ensure that memory retraining happens only first time 2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig boot twice to ensure caching of memory training occurred on each boot. Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mb/google/deltaur: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I1773973f64bcc5ef6bd1856c5d8eb998bb6a4888 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-02mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh
This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-22mb/google: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-26mb/google/deltaur: Make return values non-constJacob Garber
Returning a const uint32_t doesn't do anything, and it conflicts with the declaration of sku_id() in include/boardid.h. Change-Id: I2719e5782c9977f8ca4ce8f1dd781f092aa73d64 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1428708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44746 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable SMBus depending on devicetree configurationFelix Singer
Currently SMBus gets enabled by the option SmbusEnable, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SMBus controller. I checked all corresponding mainboards if the devicetree configuration matches the SmbusEnable setting. Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-03mb/google/deltaur: Change H1 I2C speed to FASTEric Lai
H1 is stable after HW rework. Connect +3.3V_ALW_PCH with +3.3V_PRIM. Therefore change I2C speed back to FAST. BUG=b:154885320 TEST=Check H1 I2C speed is 375kHz by scope. And no error message in cbmem and kernel log. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If58721039d90514a17f024e6b432f3a5226440e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-05-28mb/google/deltaur: Remove devicetree chip drivers/netKyösti Mälkki
Change-Id: Ia56305e9554b666f8eaf590a91be84e5cac4c75c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41701 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26mb/google/deltaur: Update audio verb table for jack detectionJairaj Arava
Additional verb changes are needed for Headset and Mic detection to work properly. BUG=b:155360937 TEST=Headset and Mic detection is working in the UI audio tray Change-Id: I184a05949f5522e929969156b72629be3d957e3f Signed-off-by: Jairaj Arava <jairaj.arava@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41642 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/intel/tigerlake: Move PMC PCI resources under PMC deviceTim Wawrzynczak
Historically in coreboot, the PMC's fixed PCI resources were described by the System Agent (the MMIO resource), and eSPI/LPC (the I/O resource). This patch moves both of those to a new Intel SoC-specific function, soc_pmc_read_resources(). On TGL, this new function takes care of providing the MMIO and I/O resources for the PMC. BUG=b:156388055 TEST=verified on volteer that the resource allocator is aware of and does not touch these two resources: ("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1") Also verify that the MEM resource is described in the coreboot table: ("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved") Verified the memory range is also untouchable from Linux: ("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved") Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mb/google/deltaur: Remove WLAN PCIE settingEric Lai
Deltaur uses CNVi WLAN module, this setting is not required. BUG=none TEST=WiFi is functional in OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idb23e271074c8d1e111c559695d4169af5e0d3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-20mb/google/deltaur: Add tcss.aslEric Lai
Add tcss.asl to support TCSS power management. For the detail please refer cb:39785. BUG=none TEST=Check TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3 /sys/bus/pci/devices/bus:device:func/power suspend and active time can increase. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I432f3d6643de13b08c07e47f799c0ecdfe047de6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41506 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mb/google/deltaur: Add low power idle tableEric Lai
Add low power idle table to notify EC system is entering s0ix. BUG=none TEST=Power button and keyboard backlight are off when suspending. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icf4dffe2bd289c15854bbad914c3b34b307254ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/41494 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18mb/google/deltaur: Remove DSP settingEric Lai
Deltaur does not use DSP so remove the DSP setting. BUG=b:155360937 TEST=Recording and playing are working fine in OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I01c076806448fc73980ec02e7558ccf082723d92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18mb/google/deltaur: Add audio verb tableEric Lai
Add audio verb table provided by vendor. BUG=b:156447983 TEST=Have beep sound when run "devbeep" in CLI. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I807d84de1677459ea027e645488f485b0ac7b2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/41401 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18mb/google/deltaur: Update audio settingEric Lai
Deltaur uses HDA codec so we need to set iDisplay Audio Codec disconnection and enable HdaAudioLink, otherwise the HDA codec won't respond to commands to execute HDA verbs. BUG=b:156447983 TEST=No timeout error when run "devbeep" in CLI. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I15d2895866abcf68963c9732ed5d05f32096fc92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41397 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14mb/google/deltaur: Configure GPIO B11 as PMCALERTAnil Kumar
GPIO B11 pin should be configured as PMCALERT function. This is required for the intergrated USB-C feature to work in the SOC BUG=b:154778458, b:156288164 TEST= build and boot coreboot image on deltan. Test Type-C port enumeration on Chrome OS Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I8f995901b0a50d2c74f57aba96f86134c9d569e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41378 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06soc/intel/tgl: Synchronize GPIO ASL table with Linux kernelShaunak Saha
Kernel pinctrl driver changed for Tiger Lake and went to old scheme. Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2116670 BUG=b:151683980 BRANCH=none TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl verify INTC34C5:00 listing all the pins. Cq-Depend:chromium:2116670 Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01mb/google/deltaur: Add BT reset gpioEric Lai
Harrison Peak (HrP) 9560 module needs a reset pin for BT power sequence. BUG=b:155248677 TEST=Boot into OS and check BT is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-01mb/google/deltaur: Update USB/WWAN configIvy Jian
Update USB3 ports configuration as schematics design. BUG=b:155026295 TEST=Boot into OS and check WWAN device detected by lsusb. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40818 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/deltaur: Disable POWER_OFF_ON_CR50_UPDATEEric Lai
This is missing configuration of Wiloc projects. Following Wilco projects configuration. CB:32436 The power architecture on this platform is different than most of our other x86 devices and needs some special handling to ensure it powers up again after an EC reset. BUG=b:150165131 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6da89de9401793a4e5c56a23c1018527819718cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40663 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/deltaur: Change H1 I2C speed to STANDARDEric Lai
Currently, Deltaur’s I2C speed has not been tuned yet, so slow down the H1 I2C to avoid I2C error for short term. Error logs: Reading cr50 TPM mode I2C receive timeout I2C read failed: bus 3 addr 0x50 BUG=b:154310066 TEST=Check H1 has no I2C error occurring and can be updated by gsctool. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I85a63c1ab9a51d254873377a36d56823af11f0a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40644 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28mb/google/deltaur: Enable PS/2 keyboardEric Lai
By default, the ACPI status method _STA returns false for the PS/2 keyboard and mouse device of the Wilco EC, so the OS does not enable it. Enable these devices, by defining the macro SIO_EC_ENABLE_PS2K. BUG=b:154790509 TEST=Check Keyboard is functional under OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I31c74ddb3608589e5a4753c7e487f250b112bb1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40745 Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-27mb/google/deltaur: Enable DRIVERS_I2C_HID for TouchpadEric Lai
Cirque touchpad uses I2C_HID driver. BUG=b:152931802 TEST=Touch pad can work well in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3f8d5abad2f153f395ba7e3f979ad3d2526e040c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-27mb/google/deltaur: Move the code under domainEric Lai
Chip drivers not overrided if out of domain. Only device can get override, so move the code under domain. BUG=b:152924290,b:152931802 TEST=Touch screen and Touch pad can work well. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iaaa73e36ec268d26ebd3cafab79179fe22a926a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-25mb/google/deltaur: Move early gpio table to variantsEric Lai
If set variant early gpio table NULL, it will override the baseboard table. Move early gpio table to variant level. BUG=b:154310066 TEST=Check H1 has no I2C error occurs. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie4c4648ccf918446a499019a4f77f64e43a92c76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-23rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGEJulius Werner
When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the appropriate calling stage (bootblock or romstage). This means that ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE are 1. This keeps tripping up people who are just trying to write a simple "are we in verstage (i.e. wherever the vboot init logic runs)" check, e.g. for TPM init functions which may run in "verstage" or ramstage depending on whether vboot is enabled. Those checks will not work as intended for CONFIG_SEPARATE_VERSTAGE=n. This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to clarify that this macro can really only be used to check whether code is running in a *separate* verstage, and clue people in that they may need to cover the linked-in verstage case as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-22mb/google/deltaur: Correct SPD SMBus addressEric Lai
SMBus uses 7-bits address, change it from 8-bits to 7-bits. BUG=b:151702387 TEST=Check Memory SPD data is correct in console log. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1720b4d6aa0bc785ad86234b3523bb0676ec5c82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-22mb/google/deltaur: Remove GbE FMAP regionTim Wawrzynczak
Deltan will be using the integrated Intel GbE for LAN functionality. Deltaur will not have a LAN port, and so does not need the GbE region. This patch adds a new FMAP descriptor file which explicitly supports the GbE region (chromeos-gbe.fmd), and removes the GbE region from chromeos.fmd. Deltan is then assigned chromeos-gbe.fmd, and Deltaur is assigned chromeos.fmd. BUG=b:150165131 TEST=emerge-deltaur coreboot chromeos-bootimage and use ifdtool -p tgl -t image-delta{ur,n}.bin to make sure FMAP aligns with IFWI Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib93d5ba7f8dbf273ba7c1163022661ede1f44ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20mb/google/deltaur: Add memory topology SODIMM and MEMORYDOWNEric Lai
Update memory topology for spd info. Deltan supports SODIMM and Deltaur supports MEMORYDOWN. BUG=b:151702387 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If314894325d6f222807030a36f8c4cefecfe5bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-20mb/google/deltaur: Correct H1 I2C gpio pin settingEric Lai
H1 uses I2C3 in the HW schematics and connects to GPP_H6 and GPP_H7. Previous setting was wrong so correct it. BUG=b:150165131 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I43c18baea66b927d51689579a40a53f72b94ef36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40487 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/deltaur: Enable Cirque touchpad for DeltanEric Lai
Reference Arcada to add device tree for Cirque touchpad. BUG=b:152931802 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia354702c8054b5826d45896f7bff268335726028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-14mb/google/deltaur: Enable Melfas touch screen for DeltanEric Lai
Reference Drallion to add device tree for Melfas touch screen. BUG=b:152924290 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-13mb/google/deltaur: Add support to enable GbE on variantVarun Joshi
- Configure devicetree for enabling GbE on variant and remove from baseboard. - Configure Kconfig to enable GbE region. - Configure fmd to incorporate GbE. BUG=b:151102809 Cq-Depend: chrome-internal:2843183 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I1c36b132546049e3e775585c41164072f4ece73e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-04-13mb/google/deltaur: Return SKU ID infoAnil Kumar
For Deltaur and Deltan variants return proper SKU ID based on EC firmware type and sensor detect GPIO value BUG=b:152544516 TEST=make build successful for deltan Change-Id: I20a497739e5062400b093648c3a634203dec6105 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-13mb/google/deltaur: Update onboard memory configVarun Joshi
Update dq, dqs map based on deltan schematics. Configure memory to read SPD. BUG=b:151702387 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30mb/google/deltaur: Provide initial devicetreeTim Wawrzynczak
This initial devicetree attempts to correctly configure the status of each PCI device. Not all required drivers are instantiated, nor are all of the SoC options fully selected yet. PCIe root ports are enabled and clocks are assigned. USB ports are assigned. BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I911ec08b0db3647d131113a138fb74a55612fd62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-03-30mb/google/deltaur: Add initial GPIO configurationTim Wawrzynczak
This configuration sets up all of the GPIO pads for the first rev of the board. BUG=b:150165131 BRANCH=none TEST=util/abuild/abuild -p none -t google/deltaur -x -a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/39674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-03-30mb/google/deltaur: add deltaur mainboard initial supportBora Guvendik
Created a new Google baseboard using Tiger Lake named deltaur, taking volteer as a starting point. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 06:49:24 +0000