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2020-09-08mb/google/dedede: Fix the SPD pathKarthikeyan Ramasubramanian
CB:44774 introduced the non-existent SPD path. This is preventing the device from booting up. BUG=b:168053219 TEST=Build and boot drawcia board to OS. Change-Id: I70ca5f4cf2c8e2e88ea5b1514b656caafb732743 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-08mb/google/dedede/var/drawcia: Configure I2C high and low timeKarthikeyan Ramasubramanian
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:162232776 TEST=Measured the I2C bus frequency as 389 KHz, high time as 870 ns and low time as 1580 ns. Change-Id: I67d2725a7fc8d83e3fa8a56cfa86540c4e6f0971 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45084 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08mb/google/dedede/var/waddledee: Configure I2C high and low timeKarthikeyan Ramasubramanian
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:163743035 TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and low time as 1680 ns. Change-Id: I60a5f6814fb9818c724f6b6fe465ea49d0de0f97 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45083 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06mb: remove duplicated Make code for spd.bin generationMichael Niewöhner
Drop duplicated code for spd.bin generation that is provided globally in lib/Makefile.inc. For all affected boards it has been verified that the output binary functionally matches the original one. The changed execution order of Make instructions influenced the cbfs file order. Hence, the rom images can't be compared directly. Thus, the output files of the two timeless abuild runs have been compared. Further, it was verified that the final files in cbfs stay identical, by comparing the extracted cbfs of each board. The boards (possibly) needing modification could be found with something like this (with false positives, though): find src/mainboard -name Makefile.inc | \ xargs egrep 'SPD_BIN|SPD_DEPS' | cut -d: -f1 | sort -u Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-31mb/google/dedede/var/drawcia: Add elan USI touchscreenWisley Chen
BUG=b:155002684 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I87d8575131e745dec818bc5864ca6b21ce0825af Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-28util: rename lp4x spds to include "lp4x-" in nameNick Vaccaro
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex). BUG=b:160157545 TEST=run gen_part_id for volteer variants and verify that it changed spd names to prepend the "lp4x-" to the filename.. Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: volteer/dedede: move generic SPDs to common locationNick Vaccaro
Now that generic SPD files have the memory type prepended to the filename, they can be stored in the same location. This CL moves the generic SPDs to the new location. Change the ddr4 gen_part_id.go and gen_spd.go tools to use "ddr4_spd_manifest.generated" instead of "spd_manifest.generated". Change the lpddr4x gen_part_id.go and gen_spd.go tools to use "lp4x_spd_manifest.generated" instead of "spd_manifest.generated". Move TGL DDR4 and LPDDR4x generic SPDs into a common location. Move JSL DDR4 and LPDDR4x generic SPDs into a common location. Change the volteer/spd/Makefile.inc to use the new path for the spds. Change the dedede/spd/Makefile.inc to use the new path for the spds. BUG=b:165854055 TEST="emerge-volteer coreboot" and verify all variants build correctly. Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/dedede/var/drawcia: Add Goodix touchscreenWisley Chen
BUG=b:155002684 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I89a4a5bbcd26b156a9660f80090bb5c953196b84 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-24mb/google/dedede: add mainboard_smi_espi_handler for dedede.Kane Chen
By adding mainboard_smi_espi_handler, the espi smi can be handled properly. BUG=b:163382105 TEST=Tested lid close smi can be handled properly in depthcharge stage Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I8a2ecb52d5f6586f8acd57c4965b4238b95e3b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44564 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/dedede/var/magolor: Add device settingsRen Kuo
Add the configuration in device tree: 1. Add HDA,speaker codec and speaker amp setting 2. Add Elan and Goodix touchscreen setting 3. Add user facing camera usb setting 4 Add Synaptics and Elan Touchpad setting 5. Add WiFi configuration BUG=None BRANCH=None TEST=build magolor firmware Change-Id: Ifc562b4a05c8955d2aec105f2f429f926ad1e702 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44633 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/dedede/variants/drawcia: add charger input current throttlingSumeet R Pawnikar
Add charger input current throttling for drawcia system BUG=None BRANCH=None TEST=Built and tested on drawcia system Change-Id: I34fdc23fcd84b5c27c2bada769f7a9049c2a56a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-22mb/google/dedede: Enable CSE Board Reset OverrideKarthikeyan Ramasubramanian
This will ensure that the cold reset is performed when CSE Lite jumps from RO to RW. BUG=b:162386991 TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP. Change-Id: I46a390c71e380328cd7fe70214df09553b2db75c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-21mb/google/dedede: Enable IPU for Wdoo and Wdee variantsMaulik V Vaghela
IPU is required to be enabled for platform supporting MIPI camera. IPU is by default disabled in devicetree for all variants. Enable IPU for Waddledoo and Waddledee supporting MIPI camera. BUG=None BRANCH=None TEST=IPU is enabled for platforms and enumerates in lspci. Change-Id: Ia3cf06d78be4301c68bfa8b1118ddff231d24a66 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44271 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-20src/mainboard: Escape variable expansion in KconfigPatrick Georgi
Kconfig 5.8 interprets $(...) itself using environment variables, which generally means that they expand to the empty string. \$(...) works with both our current and new Kconfig with the desired behavior (to pass it through unmodified). Change-Id: I726567eeb61d2035560152677d2b4548c1472be9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44584 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18mb/google/dedede: Fix S3 wake using trackpadMeera Ravindranath
Configure TRACKPAD_INT_ODL pad reset config to DEEP and map PMC_GPE_DW to PMC_GPP values. TEST=System should wake from S3 via trackpad Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-17mb/google/dedede/var/magolor: Generate SPD ID for supported partsRen Kuo
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR And also remove the deprecated by cl#43989 https://review.coreboot.org/c/coreboot/+/43989 BUG=None TEST=Build the magolor board Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I3348b7fbeff038b85e7d3c9137517e05a35bf3dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44408 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDurV Sowmya
This patch updates the SLP_Sx assertion width and power cycle duration for the dedede platforms. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159104150 TEST=Verified that the power cycle duration is ~1.2s with global reset on waddledoo. Change-Id: I7079cbd564288b5d5b69e07661434439365063d3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-14mb/google/dedede: Add a board specific resetKarthikeyan Ramasubramanian
When CSE Lite jumps from RO to RW, global reset is initiated. When AP is reset as part of global reset, TPM initialization fails. This is because AP reset is not detected by TPM hosting an older firmware version. Request Embedded Controller (EC) to perform AP reset so that TPM can detect that event. BUG=b:162290856, b:162386991 TEST=Ensure that the device boots to OS with the board-specific reset sequence when CSE Lite jumps from RO to RW with an older and newer Cr50 firmware. Cq-Depend: chromium:2337430 Change-Id: Ib1f7271130e0b4b68c7f0917ecc4eadba1486206 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-12mb/google/dedede/variants/drawcia: add DTT supportSumeet R Pawnikar
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control. BRANCH=None BUG=b:161993459 TEST=Built for dedede system Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-07mb/google/dedede/var/magolor: Select 16 MB SPI ROMRen Kuo
Decrease the SPI ROM size from 32 MB to 16 MB BUG=b:58540772 BRANCH=None TEST= build firmware and check the magolor bin size Change-Id: Ie7ddf698fde1dbf663859d5654946bc08abe737c Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-04mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03mb/google/dedede: Update CPU critical temperatureSumeet R Pawnikar
Observed thermal shutdown initiated by DPTF due to CPU temperature reaching critical temperature trip value. During stress testing with heavy workload like WebGL Aquarium, sometime CPU temperature spikes till 99 degree Celsius and DPTF initiates system shutdown. This updates CPU critical temperature trip value to 105 degree Celsius to avoid system shutdown. BUG=b:161993459 BRANCH=None TEST=Built and tested on dedede system Change-Id: If15a873a997aa80f20940f27bbafd4498908c091 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44054 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/dedede/var/madoo: Add discrete WiFi configurationDtrain Hsu
Add RTL8822CE support for Madoo. BUG=b:162390420 BRANCH=None TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage, build successful Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6e471be2b2856977e6f728d5a2ca78942725bea6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03mb/google/dedede/var/madoo: Support Elan touchpad and configure I2C portsDtrain Hsu
1. Add Elan touchpad support. 2. Follow schematic to disable I2C1 and I2C3. BUG=b:160869188,b:161407664 BRANCH=NONE TEST=emerge-dedede coreboot chromeos-bootimage", build successful Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I154a1ff2597968d200d1d0693718f90cd2744616 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03mb/google/dedede/var/madoo: Enable Goodix touchscreenIan Feng
Add Goodix touchscreen support. BUG=b:160868197 BRANCH=None TEST=emerge-dedede coreboot chromeos-bootimage", build successful Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I9bf27d69d0895cb4ea8620a6da49e98d25e05c23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44012 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30mb/google/dedede: Add Goodix touchscreenEvan Green
Add overridetree info for the touchscreen. BUG=b:160129126 TEST=cros flash-ap -b dedede Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I55fc0749b824a0bf4b615d02bd8bc39bcdd589e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-29mb/google/dedede/var/magalor: Generate SPD ID for supported partsKarthikeyan Ramasubramanian
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory part being added is: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR BUG=None TEST=Build the magalor board. Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-28mb/google/dedede/var/madoo: Generate SPD ID for supported partsDtrain Hsu
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: H9HCNNNBKMMLXR-NEE MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR BUG=b:161215903 BRANCH=NONE TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib61af2399541c4caf4a310a34e778e0ba1cbd3ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/43802 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/dedede/var/madoo: Add audio support (ALC5682, MX98360A)Dtrain Hsu
Select the drivers for ALC5682 codec and MX98360A spk amp BUG=b:161407664 BRANCH=NONE TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ibe3d878b1058bfae4143d96be854884e61394ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-28mb/google/dedede/var/madoo: Configure USB port setting for MadooDtrain Hsu
Follow schematic to modify USB port setting and clean up I2C clock tuning. USB2 [0]: USB Type C Port 0 USB2 [1]: USB Type C Port 1 USB2 [2]: None USB2 [3]: USB Type A Port 1 USB2 [4]: None USB2 [5]: Camera USB2 [6]: None USB2 [7]: WLAN module - BlueTooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: USB Type C Port 1 (Sub/B side) USB3 [2]: None USB3 [3]: USB Type A Port 1 USB3 [4]: None USB3 [5]: None BUG=b:161407664 BRANCH=NONE TEST=Build the coreboot image on madoo board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ia73593f52adee3806e725127891f084a08bf1360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43750 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/dedede/var/madoo: Configure GPIO for MadooDtrain Hsu
Follow schematic to modify some GPIO pins. GPP_D12 - NC Pin GPP_D13 - NC Pin GPP_D14 - NC Pin GPP_D15 - NC Pin GPP_E0 - NC Pin GPP_E2 - NC Pin GPP_H6 - NC Pin GPP_H7 - NC Pin GPP_S02 - NC Pin GPP_S03 - NC Pin BUG=b:161407664 BRANCH=NONE TEST=Build the coreboot image on madoo board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I85aadfb0d020055eec921c7646c16ae6c95a606f Reviewed-on: https://review.coreboot.org/c/coreboot/+/43745 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/dedede/var/waddledee: Add discrete WiFi configurationKarthikeyan Ramasubramanian
BUG=b:161734657 TEST=Ensure that the discrete WiFi information is built into ACPI table. Scope (\_SB.PCI0.RP01) { Device (WF00) { Name (_UID, 0x923ACF1C) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x43, 0x03 }) } } Change-Id: I9a9259e167fc213291b89e151729553ec4649eaf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43769 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27mb/google/dedede: Remove Rcomp resistor and target valuesMeera Ravindranath
MRC automatically detects the DDR type and sets Rcomp resistor and target values for JSL and does not require explicit programming. Change-Id: Ia130765e2cb91d6a39ad00ebbab20e7e87fa42d1 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27dedede: Create magolor variantRen Kuo
Create the magolor variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:58540772 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_MAGOLOR Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I3e39e650b82a0aa629a48a00227700b058effb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-26mb/mainboard/dedede: update GPIO table for Botenyan.liu
Adjust GPIO setting to match boten design BUG=b:160741777 BRANCH=NONE TEST=Add gpio.c for boten Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com> Change-Id: I4eafee608f657f8ec5a06caf6e99b08b3330512b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43277 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/google/dedede: Change HDMI DDC GPIOs to native functionMaulik V Vaghela
HDMI DDC GPIOs were configured as NC till now in waddledoo. This may cause HDMI i2c transfer to break and EDID read will fail due to wrong configuration Configuring these GPIOs as NF in coreboot to fix the issue. BUG=b:160324327 BRANCH=None TEST=HDMI works on DDI2 onn Type-C port Change-Id: If02f062132d7c3b01b07ea9401e81f451df35c3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43294 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src: Remove unneeded space in license headerElyes HAOUAS
Change-Id: Iac0f0c3d102a9a900ac168f8be907349d9a3dd42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43565 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/google/dedede/var/drawcia: Add G2Touch touchscreen supportWisley Chen
BUG=b:155002684 TEST=build drawcia, and check touchscreen can work Change-Id: I29a891e07bb3c1d8ebe17666c18bfcf3bc1c361d Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/dedede/var/waddledoo: Configure stop delay for SiS TSKarthikeyan Ramasubramanian
Reset the Touchscreen (TS) and disable the stop GPIO (report switch) at the same time. Add a delay of 100 ms after disabling the stop GPIO. This will ensure the required delay is inserted for both reset and stop disable GPIOs simultaneously. BUG=b:152936541 TEST=Build and boot the waddledoo mainboard. Ensure that the SiS Touchscreen is functional. Change-Id: Icbfb5e07a28ab72b1ff696ad1183a6c2173dcaac Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43453 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/dedede/var/drawcia: Generate SPD ID for supported partsKarthikeyan Ramasubramanian
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR BUG=None TEST=Build the drawcia board. Change-Id: Id05c0b2a87b64bfedc761949cbc8ad6cf7dd73a5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43505 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/dedede: Enable the CSE Lite SKU for dededeV Sowmya
This patch enables the CSE Lite SKU for the dedede baseboard. BUG=b:160201335 TEST=Build and boot waddledoo with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I24d7d715d55524807af0127aa4a346a008164b8c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-23mb/google/dedede: Skip the CPU replacement check for dededeV Sowmya
This patches enables the SkipCpuReplacementCheck config for the dedede baseboard to avoid the forced MRC training for all its variants with the soldered down SOC. BUG=b:160201335 TEST=Build and verify CSE Lite SKU on Waddledoo. Cq-Depend: chrome-internal:3142530 Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-21mb/google/dedede: Create madoo variantIan Feng
Create the madoo variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:161191394 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_MADOO Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I6d3f611606f86036d67be9c8b0fda833ab61ecc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-20mb/google/dedede: Update link frequency and end point structure for OV9734Pandya, Varshit B
1. Update Link frequency to 180 Mhz 2. Set data-lanes to 1 and 3. Update the clock-lane used by sensor BUG=b:155285666 BRANCH=None TEST=Build and able to capture image using user facing camera. Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Change-Id: I164cb6af1003de561be8ce640e7653b7bcb3a22f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-07-18mb/google/dedede: Convert static DPTF ASL into devicetree entriesTim Wawrzynczak
Since there is now a mechanism to generate DPTF ACPI tables and methods at runtime, dedede should switch to using that instead of raw ASL files. This patch converts the existing .asl files into devicetree entries. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/dedede: Enable SIS touchscreen for WaddledeeKarthikeyan Ramasubramanian
Add SiS9813 USI touchscreen support. BUG=b:160129126 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Change-Id: I42fdc5e8243d2c70c953b2f516c10f84a041c035 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43304 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/google/dedede: Add ability to provide override GPIO tableKarthikeyan Ramasubramanian
For variants with slightly different GPIO configuration, add support to pass an override GPIO configuration table. BUG=None TEST=Build and boot the waddledee mainboard. Change-Id: I2f1c6dc2ea5499bff96a471c4461339ef01ee19a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-12mb/google/dedede/var/drawcia: support internal usb cameraWisley Chen
BUG=b:160741778 TEST=build drawcia, and check camera can be regconized Change-Id: I67bee9773b53451653abd76088d1d4062fe3da8f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42929 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/google/dedede/var/drawcia:Add audio support (ALC5682 codec, MX98360A spk amp)Wisley Chen
Select the drivers for ALC5682 codec and MX98360A spk amp BUG=b:158202026 TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage Change-Id: If271f11f10a85ade6f61ff8c25bfafeb67a69af6 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-08mb/google/waddledee: Enable AudioMaulik V Vaghela
1. Enable HDA Pci device in devicetree 2. Enable I2C4 in devicetree and fill ACPI information 3. Pass correct IRQ GPIO for headset jack BUG=None BRANCH=None TEST=Audio playback and recording works on Waddledee. Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Yong Zhi <yong.zhi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41765 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/dedede/var/drawcia: add elan touchscreenWisley Chen
BUG=b:155002684 TEST=build drawcia, and check touchscreen can work Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-08mb/google/dedede/var/drawcia: Support Elan touchpadWisley Chen
BUG=b:155002811 TEST=build drawcia, and check touchpad can work. Change-Id: I674236aa6937a0444a85e6b8e2fb9a7925b56f5c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42922 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/dedede: Create Boten Legacy variantKarthikeyan Ramasubramanian
Upcoming builds of boten will use 16 MiB SPI ROM. So create a legacy Boten variant to support the builds that use 32 MiB SPI ROM. BUG=None TEST=Build the boten and boten_legacy variant. Cq-Depend: TBD Change-Id: Idf7732768aa7fbf2281a4cbf47b7b5b4f8ef51da Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-06mb/google/dedede: Create Drawcia Legacy variantKarthikeyan Ramasubramanian
Upcoming builds of drawcia will use 16 MiB SPI ROM. So create a legacy Drawcia variant to support the builds that use 32 MiB SPI ROM. BUG=None TEST=Build the drawcia and drawcia_legacy variant. Cq-Depend: TBD Change-Id: Ifb5a4778abe38a396e35963a3270b0d3cc9809e0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-01mb/google/dedede: set tcc_offset value to 10Sumeet R Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. BUG=None BRANCH=None TEST=Built for dedede platform and verified the MSR value Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42906 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24jasperlake: enable DPTF functionality for dededeSumeet R Pawnikar
Enable DPTF functionality on jasperlake based dedede platform BRANCH=None BUG=None TEST=Built for dedede system Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/dedede: Re-configure the USB ACPI objectsKarthikeyan Ramasubramanian
In waddledee and waddledoo, discrete & integrated BT signals are routed to different USB ports. In all the other variant boards, discrete & integrated BT signals are routed to the same USB port (port 8 - index 7). Re-configure the USB devices accordingly. Also device configuration in override tree are applied only if there is a matching device in base devicetree. So configure all the USB devices in base devicetree and turn them off. BUG=b:154064148 TEST=Ensure that the SSDT contains the ACPI objects for enabled USB devices. Change-Id: I1b8bf7f4db1d2661f310bf4874428a6d1de222c6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42554 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/dedede: Add VCM and NVM entry for OV8856 sensorPandya, Varshit B
Add DW9768 VCM device and add its entry in the OV8856's _DSD to allow the V4L2 driver to use the VCM functionality. Also add ACPI entries for AT24 NVM device, this will enumerated as a generic NVM device and not part of the V4L2 framework. BUG=b:155285666 BRANCH=None TEST=Build and able to see DW9768 and AT24 getting listed I2C3 lanes and able to capture image using world facing camera. Change-Id: I19e4a4107c5bc9d96f718d654df50e2705b98c03 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-18mb/google/dedede: Add support for 16 MiB flash map descriptorKarthikeyan Ramasubramanian
Upcoming variant boards will use 16 MiB SPI ROM. So add support for 16 MiB flash map descriptor. BUG=b:155107866,b:152981693 TEST=Build different variant boards. Ensure that waddledoo which is using 32 MiB SPI ROM boots. Cq-Depend: chrome-internal:3107306 Change-Id: I8a6868da3280a662ff3a30623804ff135e6cbfbc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14mb/google/dedede: Enable early EC software syncMeera Ravindranath
BUG=none BRANCH=none TEST=Verify sysjump from EC console, EC sync in romstage in AP console and crossystem reflect ecfw_act as RW Change-Id: Ief96fe481c94acef3754881cf1f453699fbfa52e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41396 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/dedede: Select Recovery Cache Kconfig optionMeera Ravindranath
BUG=none BRANCH=none TEST=Boot WaddleDoo in recovery and populate the recovery MRC cache. The subsequent recovery boot should boot out of the stored recovery MRC cache and skip memory training. Change-Id: Ief86fe481c94abef3754881cf1f454699fbfa52e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41162 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/dedede: Add new variant botenPeichao Wang
Add initial support for boten variant board. BUG=b:158023819 BRANCH=None TEST=build Change-Id: I56fe901c6aec781fac217ab08f7583cc25788688 Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-06-11mb/google/dedede: Add new variant drawciaWisley Chen
Add initial support for drawcia BUG=b:158540280 BRANCH=None TEST=build Change-Id: Ic775bb2a93581e422379ca90127e3581bbf3c89e Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-06-10mb/google/dedede/variants/waddledoo: Adjust I2Cs CLK to meet specJohn Su
After adjustment on waddledoo Touch Pad CLK: 392.9 KHz Touch Screen CLK: 387.4 KHz Audio CLK: 350.9 KHz BUG=b:151302522 BRANCH=master TEST=emerge-dedede coreboot chromeos-bootimage measure by scope with waddledoo. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iec02a751f1effdbefbb2969db2fd57f27ecdd033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42187 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10mb/google/dedede: Enable S0ix supportAamir Bohra
Change-Id: I4cadfe69e36f959b54e374800c32629a7481ea94 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-10mb/google/dedede: Add mainboard acpi support for GPIO PM configurationAamir Bohra
Setting the default values for GPIO community power management, causes issues in detecting TPM interrupts. So to avoid that GPIO PM has to be disabled in devicetree. But for S0ix it is needed. This patch implements a workaround in ASL code to enable GPIO PM on S0ix entry and disable it on S0ix exit. This patch adds the following three platform specific methods. 1. MS0X to enable power management features for GPIO communities on low power mode entry and disables it on exit. 2. MPTS to enable power management features for GPIO communities when preparing to sleep. 3. MWAK to disable power management features for GPIO communities on waking up. BUG=b:153847814 TEST=Verify S0ix is working. GPIO PM configuration is upadated on low power mode entry and exit. Change-Id: I7225b78ab2ac5bf17f93230cd85cd21e836d807d Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41502 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08mb/google/dedede: Default spk_en gpio to lowUsha P
The max98357a_platform_driver will turn on/off the speaker enable gpio based on use, so configure it low to save power. BUG=None TEST=Built dedede and tested speaker playback working. We are seeing a power saving of ~10mW. Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-06-08mb/google/dedede: source soc_common_config from variants overridetreeMaulik V Vaghela
All variants are overriding soc_common_config, so source it from overridetree and remove entry from baseboard devicetree. Only keeping chipset lockdown config in baseboard which will be common across all the variants. BUG=None BRANCH=None TEST=Checked code compilation and lockdown config is applied to all variants Change-Id: I23714b721a6bb0bac785f046586790a98dc5b646 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-06-07soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI deviceTim Wawrzynczak
This change allows treating the PMC as a 'hidden' PCI device on Jasper Lake, so that the MMIO & I/O resources can be exposed as belonging to this device, instead of the system agent and LPC/eSPI. Change-Id: Ie07987c68388d03359c43f64a849dc6e3f94676e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-06mb/google/dedede/var/wheelie: Add memory parts and generate DRAM IDsFurquan Shaikh
This change adds memory parts used by variant wheelie to mem_list_variant.txt and generates DRAM IDs allocated to these parts. BUG=b:157862308 Change-Id: I53f6f5c832cd40068a6d4379ace849f6e8ad7a91 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41990 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede: Drop .spd.hex files from spd/Furquan Shaikh
Now that dedede is moved to using the auto-generated SPDs, we no longer need the .spd.hex files in spd/ folder. Hence, this change drops the files. Change-Id: I026b3c61a2a88a7cd2c9842a26eb336324853add Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41882 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede: Switch to using auto-generated SPDsFurquan Shaikh
This change switches dedede and family to using auto-generated SPDs obtained using gen_spd.go and gen_part_id.go. Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41881 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede: Drop selection of GENERIC_SPD_BINFurquan Shaikh
GENERIC_SPD_BIN assumes that the SPDs are all placed in mainboard and have .spd.hex as the suffix. Disable GENERIC_SPD_BIN for dedede as it already provides its own rules for SPD inclusion. In follow up changes, GENERIC_SPD_BIN can be re-enabled by updating gen_spd.go tool to use similar suffixes and allowing different paths to be provided for SPD by mainboard. Change-Id: If10144e0b2bd67884af69f60e5117e388a3ae5da Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42054 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledoo and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Waddledoo started assigning DRAM part IDs from 1. So, this change fills in Nanya part as ID 0 (though it is currently unused). Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/dedede/var/wheelie: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by wheelie and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Change-Id: If307bfb1d376e32af08af4f020f9e125f6a415dd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/dedede/var/waddledee: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledee and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Byte# Current New Explanation 4 0x14 0x15 This part has only 1 die. Hence, density per die is 8Gb. 6 0x90 0x04 1 die in package and 2 channels per die. Manufacturer name bytes are set to 0. Change-Id: I7a68a29ca3632e22f3960c9fc44acf3ce4f87c9c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/dedede/board_info.c: Clean upElyes HAOUAS
Remove unused includes Change-Id: I7e8109870168db7f477f205a0b3020b7b2be5f5f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41541 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03Makefile: Drop HAVE_SMI_HANDLER test for smm-classKyösti Mälkki
Change-Id: Id0bb5266246dbd959c6497d7c411f908cc49318c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-02mb/google/dedede: Enable GBB configs for dededeUsha P
This patch enables the necessary GBB configs for dedede BUG=none BRANCH=none TEST=GBB Flag value was 0x39 before enabling the required flags and now it is updated to 0x40b9. Verfied from CPU log. Change-Id: Ica07c65d6cf23ea859de6aa8413377661547e47a Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2020-06-02mb/google/dedede: Add SD card supportAamir Bohra
1. Configure SD card GPIOs. 2. Set SD card power polarity and card detect configs. SD card CMD. DATA and CLK GPIOs are set for native pad termination as per recommendation in EDS vol1 section 10.4.10 BUG=b:150872580 TEST=Verify SD card enumeration and read/write transactions. Change-Id: I90c8ceb85ada23718ff7b6fd7013317c818dd532 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02mb/google/dedede: Enable coreboot lock down configAamir Bohra
TEST=Build and boot waddledoo board Change-Id: Ic10af9a0d50946a98a5c4a77b492d242cef171ca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41535 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29mb/google/dedede: Enable Heci1 deviceAamir Bohra
Enable heci1 device from devicetree for PCI enumeration. This is required for ME status dump using HFSTSx resgisters in PCI config space. Heci1 device is later disabled through heci disable flow. TEST=Build, boot waddledoo. ME status dump is seen in console logs. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-29mb/google/dedede: add new SPD SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16Marco Chen
The first DRAM part supported by SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 is NT6AP256T32AV-J2 so the SPD content is generally extracted from it's SPD. On the other hand, SPD bytes 4 / 6 / 13 were amended to follow SoC's requirement. BUG=b:152277273 BRANCH=None TEST=build the image successfully. Change-Id: If6fb0855a961d1c68315a727466bf45569cf2597 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41813 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/dedede: Enable Intel Speed Shift TechnologyKarthikeyan Ramasubramanian
Enable Intel Speed Shift Technology (ISST) by default. Disable ISST in waddledee and waddledoo variants on early phases. BUG=b:151281860 TEST=Build and boot the mainboard. Ensure that cpufreq driver to configure P-states is enabled in kernel on boards where board version is provisioned. Change-Id: Id65d7981501c2f282e564bfc140f8d499d5713e8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-05-18src: Remove unused 'include <string.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18mb/google/dedede: update SPD name based on DRAM characteristicMarco Chen
The index of DRAM_STRAPS indicates to a specific DRAM characteristic instead of a DRAM part number therefore update the existing DRAM SPD binary to the naming by DRAM characteristic. BUG=b:152019429 BRANCH=None TEST=build the image and verify that coreboot log shows the correct SPD info Change-Id: I8ffcf156f37a465209740c5e2a34effb5f1f5d5c Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13mb/google/dedede/variants/waddledoo: Modify ELAN touchscreen slave addressIan Feng
Modify ELAN EKTH6918 USI touchscreen slave address to 0x10. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I999967b0f37c82ff7811e3b6117baab795a11195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetreeKarthikeyan Ramasubramanian
BUG=None TEST=Build and boot the mainboard. Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41037 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04mb/google/dedede: Read DRAM part number from CBIMarco Chen
The index of MEM_STRAPS will be migrated from per DRAM part number to per DRAM characteristic therefore one index mapped to a single SPD binary can represent to multiple DRAM part numbers as long as their characteristic is the same for DRAM controller to support. In this case, the real DRAM part number would be provisioned in the CBI instead of SPD in the factory flow. As a result, we need to extract DRAM part number from CBI. BUG=b:152019429 BRANCH=None TEST=1. provision dram_part_num field of CBI 2. check DRAM part number is correct in SMBIOS for memory device Change-Id: I40780a35e04efb279591e9db179cb86b5e907c0d Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01mb/google/dedede: Fix crossystem wpsw_cur errorSubrata Banik
Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community zero. TEST=Build coreboot, flash, boot to and log into kernel, execute "wp enable" in console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/google/dedede: Enable USB port for camera supportIan Feng
Support USB Chicony user facing camera. BUG=b:155109736 BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using user facing camera. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I7580a58086977e239dca49c1def4f03583831662 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mb/google/dedede: Remove pad termination for RAM_STRAP_4Karthikeyan Ramasubramanian
The stuffed resistor straps are weaker compared to the internal pull-up. This can cause the GPIO to read '1' always. Remove the internal pull-up. Also read the GPIO only on the boards where the board version is populated. BUG=b:154301008 TEST=Build and boot the mainboard. Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01mb/google/dedede: Enable camera support for waddledooPandya, Varshit B
BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: I51dcf96a82535fc1e0b9247fd52af919885575e5 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mb/google/dedede: Add ACPI support for cameraPandya, Varshit B
1. Add support as per the schematics 2. Add 2 Ports and 2 Endpoints 3. Add support for OTVI8856 and OTVI5676 4. Add ON and OFF logic as Power Rails are same for both sensor BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: Ic8687bce4896d9fc17b2190b8d11618af3515cc1 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>