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Create a new config option to indicate that a board has Google Strauss
keyboard. The scan code for Fn key will be set to 94 if the new config
is selected.
Previously each board was setting the integer config option for Fn key
scan code which was not scalable. The new option is a bool and can be
easily selected by different boards.
BUG=none
TEST=Verify coreboot.config before and after this change.
Change-Id: I2b5d54879d415e4403b2d7948432bb06ab983b86
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85109
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Realtek AX generation IC utilizes LTR-issued latency requests to
optimize WiFi latency and power consumption, it requires host
enabling LTR to meet the design requirement. We enabled the host's
LTR by enabling PCIe root port 8, which met resltek's technical
requirements.
BUG=b:377400590
TEST=Tested on Drawman with RTL8852BE
Use command $ lspci -vv, LTR+ is listed on DevCtl2
BRANCH=firmware-dedede-13606.B
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85011
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Realtek AX generation IC utilizes LTR-issued latency requests to
optimize WiFi latency and power consumption, it requires host
enabling LTR to meet the design requirement. We enabled the host's
LTR by enabling PCIe root port 8, which met resltek's technical
requirements.
BUG=b:366383364
TEST=Tested on Awasuki with RTL8852BE
Use command $ lspci -vv, LTR+ is listed on DevCtl2
Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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ext_vr_update should be run after board version 0xb, but skipped by
return. Drawper LTE board version was set after 0x9, but there are more
board added after that. Specific Drawper board version as 0xa, 0xb and
0xf.
BUG=b:376828839
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage and test on DUTs.
Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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1. Modify the I2C frequency of the touchpad between 380 Khz and
400 Khz to meet the spec.
2. Increase clk the time of high (TH) to greater than 600ns.
Before:
I2C0 - 420KHz
TH - 557ns
After:
I2C0 - 398Khz
TH - 630ns
BUG=b:351968527
TEST=Check that the wave form meets the spec.
Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84898
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Add wifi PCIe hosts M.2 E-key WLAN to fulfill
drawman_jsl_schematic_20200528.
BUG=None
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: If414ff1941d2d70c5f0444ac58b228ed5c95303a
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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As per commit 865173153760 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.
Change-Id: Ia793666fda47678764fd33891fddb4aecf207bd4
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Due to beadrix DB has C1 port before, and add FW_CONFIG without C1 port for LTE sku.
BUG=b:364431483
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Set fw config to DB_PORTS_LTE and check
1.fw_config match found: DB_PORTS=DB_PORTS_LTE <= show LTE present message
2.USB3 port 3: enabled 1 <= LTE port enable
Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84232
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Reduce resume time.
BUG=b:361728839
TEST=emerge-dedede coreboot chromeos-bootimage
& test touchscreen function on awasuki DUT
Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84196
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Modify DPTF parameters from thermal team.
1. Add TCHG.
2. Modify the charging limit.
BUG=b:360066326
TEST=Modify Thermal according to design requirements
Change-Id: Ia7050b552656a70da0c992e4f54b02ccb6a7c114
Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83929
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar
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Enable Intel CrashLog diagnostic feature by default on all Google
Dedede variants.
BUG=b:354834461
TEST=Built for Google Dedede and verifed that CrashLog is enabled by
default.
Change-Id: Ib0487bd6a5bfdad2a80fd0787e009e48f4527d38
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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Before:
I2C2 - 431KHz
I2C4 - 413KHz
After:
I2C2 - 364KHz
I2C4 - 370KHz
BUG=b:351968527
TEST=Rate of the actual measured machine is pass.
Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c
Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83906
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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The AP console log contains "HECI: No CSE device" and the system cannot be entered.
BUG=b:359474142
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
The "HECI: No CSE device" message for AP log disappered
Change-Id: I488056dc8bca2174dd96c28793e3202b7aae890c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83905
Reviewed-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The Fn key on awasuki emits a scancode of 94 (0x5e).
BUG=b:355538142
TEST=Flash awasuki, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: Ic7aa183bf314fed4901133dc70d848d84fab0784
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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1. Change driver form i2c/hid to i2c/generic.
2. Add fw_config for touchscreen.
BUG=b:351968527
TEST=ectool cbi set 6 0x0x10200a0;
touchscreen functions normally;
Change-Id: Ifd6330be8924d4873f0efab3ce404168a62099eb
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83704
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because Awasuki doesn't have SD card, disable related configurations.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: I1b0d2a9c2f9cdd4bca7c30cdc454ffa84b293146
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83706
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Initialise overridetree based on the schematics revision 20240715.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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No need to have separate sections, and will be cleaner when adding
another section in a subsequent patch.
Change-Id: I4ad6be9dd67b5adbc9c5b0fcab51ce0c54351173
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Configure GPIOs according to schematics revision 20240712.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: Ic8f346b788b489f50ab96c0ace8541720a832f72
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83449
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Vendor DRAM Part Name Type
SAMSUNG K4U6E3S4AB-MGCL LP4X
SAMSUNG K4UBE3D4AB-MGCL LP4X
MICRON MT53E1G32D2NP-046 WT:B LP4X
BUG=b:351968527
TEST=Run part_id_gen tool without any errors
Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83427
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create the awasuki variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:351968527
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_AWASUKI
Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add FW_CONFIG for no port LTE skus, and probe LTE port in devicetree.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I5235df33a36f3b9472ee8b615e4622f6ee3fb1a4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add bookem new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.
Zilia SDVB8D8A34XGCL3N3T
BUG=b:344482259
TEST=Use part_id_gen to generate related settings
Change-Id: I1cbf641e2bbe4fd4eea02a1bfa3d6b3c06e567e4
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82783
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Probe C1 port in devicetree and disable un-used C1/A1 port by FW_CONFG.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I944ff6f2fa712e7579ed1c9879f75835adc3ac4c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix
H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these
parts.
DRAM Part Name ID to assign
MT53E512M32D1NP-046 WT:B 0 (0000)
H54G46CYRBX267 0 (0000)
BUG=b:337173071
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run \
./util/spd_tools/src/part_id_gen/part_id_gen.go \
JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Probe usb ports by FW_CONFIG setting to disable C1 port on
beadrix poin2 new daughterboard without C1 port.
BUG=b:316365055
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot
Change-Id: I494a922d2b04dcf7bd35680f5d95f8463e225f2d
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add beadrix supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. CXMT CXDB4CBAM-ML-A
BUG=b:321830738
TEST=Use part_id_gen to generate related settings
Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Select this at the SoC level (like other modern Intel SoCs), and drop
it from individual boards which selected it.
Change-Id: I8ebb915fbc21f82e39304473b0fcaa620559b5d5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80558
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I7230bb8f9883f186c10f41132a2919c3fd99f8c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I245eb8a9961e3e0025c0275f306a4d989b532331
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80491
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2909375d38c37332293bd7928ae33d5bb502694f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80490
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Vbt data files extracted from dedede recovery image 120.0.6099.272.
Change-Id: I28485d501e519cdaa06c55c20eba07190c5c6b6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Add the new memory support:
Samsung K4U6E3S4AB-MGCL
BUG=b:320137193
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go JSL lp4x \
src/mainboard/google/dedede/variants/galtic/memory/ \
src/mainboard/google/dedede/variants/galtic/memory/\
mem_parts_used.txt"
Change-Id: I3f6c784a194e141a3dd1e5a37b3cf12106e692d6
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80150
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
and amplifier
Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB"
BUG=b:183305590
TEST=ALC5682I-VD and ALC1015Q-VB can work normally
Change-Id: I4f212f063a1180d7a1c14769f61b0afef7565cad
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79831
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that the files are renamed, make sure all references to Makefile.inc
are updated as well.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I134acc26c0a79d974a6dd0a3b257f961db7e2d86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80106
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Repo sync code recently, run command as memtioned in TEST and
found the changed for the auto-gen files.
Then correct the memory typo from K4UBE3D4AA-MGCR to K4U6E3S4AA-MGCR,
and no new for the used hex file.
BUG=b:320181366
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go JSL lp4x \
src/mainboard/google/dedede/variants/galtic/memory/ \
src/mainboard/google/dedede/variants/galtic/memory/\
mem_parts_used.txt"
Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79976
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1. Describe the FW_CONFIG probe for the settings for Palutena.
- WIFI_SAR_ID_0 for AW Wi-Fi module AW-CM421NF
- WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW
2. In contrast to the AW Wi-Fi module, the Intel Wi-Fi module needs
to load a SAR table in dedede platform.
3. For Palutena project, the SKU ID segment of Palutena is set for
"0x350000~0x35FFFF".
BUG=b:319792428
BRANCH=firmware-dedede-13606.B
TEST=build pass
Change-Id: Ic4f38928d24c4398d90df226cfe0788a30075bf2
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79930
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
|
|
Change-Id: I09dd5871cb366ef95410efc1ca6c4337f23b52fd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79912
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Create the dita variant of the taranza project by
copying the files to a new directory named for the variant.
BUG=b:317292413
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_DITA
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79655
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
|
|
The original DA7219 is designed to use a 500ohm mic detection
threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be
detected. Lower the threshold to 200ohm to match the new default
value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets.
BUG=b:314062160,b:308207450
Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add support for the new memory CXMT CXDB4CBAM-ML-A.
BUG=b:304932936
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run \
./util/spd_tools/src/part_id_gen/part_id_gen.go \
JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
And confirm the mainboard boot normally with CXMT
CXDB4CBAM-ML-A memory.
Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78892
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This patch adds the required FMD changes to support the change
in cse_lite 'commit Ie0266e50463926b8d377825 ("remove
cbfs_unverified_area_map() API in cse_lite")' for CBFS verification.
With the change in cse_lite the ME_RW_A/B blobs are now part of
FW_MAIN_A/B and corresponding entries in FMD can be removed for boards
that currently use them.
BUG=b:284382452
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
It's not needed to put a backslash at the end of a line for quoted
multiline values. Thus, remove it.
Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Some Type-C monitors do not immediately assert HPD. If we enter FSP-S
before HDP is asserted, display initialisation may fail. So wait for
HPD.
This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP
output on cold boots") on puff, except we don't use
google_chromeec_wait_for_displayport() since that EC command was removed
for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals
only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if
HDMI is connected, which is the same behaviour as puff and fizz.
BUG=b:303533815
BRANCH=dedede
TEST=On dexi, connect a display via a Type-C to HDMI dongle and check
the dev and recovery screens are now displayed correctly. Also check the
logs in the following cases:
Cold reboot in dev mode, Type-C to HDMI dongle:
HPD ready after 800 ms
Warm reboot in dev mode, Type-C to HDMI dongle:
HPD ready after 0 ms
Cold/warm reboot in dev mode, direct Type-C:
HPD ready after 0 ms
Cold/warm reboot in dev mode, direct HDMI:
HPD ready after 0 ms
Cold/warm reboot in dev mode, no display:
HPD not ready after 3000 ms. Abort.
Change-Id: Ib4fc071cac98a542072ffbeb6943bff4c988554c
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78450
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update Goodix touchpad HID to GDIX0000 for GXTP7288 and GXTP7863.
BUG=b:305118852
BRANCH=firmware-dedede-13606.B
TEST=Build and touchpads are workable
# evtest for GXTP7863
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0: Lid Switch
/dev/input/event1: Power Button
/dev/input/event2: AT Translated Set 2 keyboard
/dev/input/event3: cros_ec_buttons
/dev/input/event4: Elan Touchscreen
/dev/input/event5: GDIX0000:00 27C6:0D51 Mouse
/dev/input/event6: GDIX0000:00 27C6:0D51 Touchpad
# evtest for GXTP7288
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0: Lid Switch
/dev/input/event1: Power Button
/dev/input/event10: GDIX0000:00 27C6:01F5 Touchpad
/dev/input/event11: sof-da7219max98360a Headset Jack
/dev/input/event12: sof-da7219max98360a HDMI/DP,pcm=2
/dev/input/event13: sof-da7219max98360a HDMI/DP,pcm=3
/dev/input/event14: sof-da7219max98360a HDMI/DP,pcm=4
/dev/input/event2: AT Translated Set 2 keyboard
/dev/input/event3: cros_ec_buttons
/dev/input/event4: ELAN900C:00 04F3:2E5D
/dev/input/event5: ELAN900C:00 04F3:2E5D UNKNOWN
/dev/input/event6: ELAN900C:00 04F3:2E5D UNKNOWN
/dev/input/event7: ELAN900C:00 04F3:2E5D Stylus
/dev/input/event8: ELAN900C:00 04F3:2E5D Stylus
/dev/input/event9: GDIX0000:00 27C6:01F5 Mouse
Change-Id: Id2a6223bdbb2f0693149136baa853ca2efb57815
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Some Type-C monitors do not immediately assert HPD. If we enter FSP-S
before HDP is asserted, display initialisation may fail. So wait for
HPD.
This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP
output on cold boots") on puff, except we don't use
google_chromeec_wait_for_displayport() since that EC command was removed
for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals
only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if
HDMI is connected, which is the same behaviour as puff and fizz.
TEST=On dibbi, connect a display via a Type-C to HDMI dongle and check
the dev and recovery screens are now displayed correctly. Also check the
logs in the following cases:
Cold reboot in dev mode, Type-C to HDMI dongle:
HPD ready after 800 ms
Warm reboot in dev mode, Type-C to HDMI dongle:
HPD ready after 0 ms
Cold/warm reboot in dev mode, direct Type-C:
HPD ready after 0 ms
Cold/warm reboot in dev mode, direct HDMI:
HPD ready after 0 ms
Cold/warm reboot in dev mode, no display:
HPD not ready after 3000 ms. Abort.
Change-Id: Id4657b5d5a95a68ecbd9efcf3585cf96ad1e13e1
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
Create the dexi variant of the taranza project by
copying the files to a new directory named for the variant.
BUG=b:303533815
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_DEXI
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I708a16cb864dca7309cb0201e7887af7456a4885
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78249
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for
enable USB wake.
BUG=b:302230434
TEST=Verify USB-A device could wake up Boxy
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78144
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake.
The physical USB slot is 6, USB2 port5 for Bluetooth, total USB2 port num is 7, USB3 keep 6.
BUG=b:300844110
TEST=Verify USB-A device could wake up Taranza
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ied92c4a70bc594bd189dcb942f1a445412509464
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78068
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I5527d5968be35f52b912d9d6e1d9f46f24569bbc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Convert TPM functions to return TPM error codes(referred to as
tpm_result_t) values to match the TCG standard.
BUG=b:296439237
TEST=build and boot to Skyrim
BRANCH=None
Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Convert hex print values to use the %#x qualifier to print 0x{value}.
BUG=b:296439237
TEST=build and boot to Skyrim
BRANCH=None
Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add PLx from JSL PDG (ID: 613095) in taranza devicetree.
Add ramstage.c in Makefile.inc and update Taranza power limits in
taranza ramstage.c.
BUG=b:296004956
TEST=emerge-dedede coreboot and check psys and PLx value on taranza
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Id43bb91bc9efb91cb074b075122cce4f22e0716c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Dedede boards which select AUDIO_AMP_UNPROVISIONED via fw_config use
rt1015 for the speaker topology, not max98360a.
TEST=build/boot Win11 on google/magpie, verify correct audio profile
selected.
Change-Id: I5b75bd8fd37d2837de3c5bd25a02411a6982103b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
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Make naming convention consistent across all functions return values.
BUG=b:296439237
TEST=Boot to OS on Skyrim
BRANCH=None
Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update PLDs to match the port layout:
Front (left to right):
A4, A3, A2
Back (left to right):
C0, A0, A1
BUG=b:264960828
TEST=USB2 and USB3 ports are peered correctly in the kernel:
Before:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port2
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6
After:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port7/peer -> ../../../usb2/2-0:1.0/usb2-port2
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port7
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4
Change-Id: I682a153d6b757e1b66373c622a6fcfbf389184e3
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77877
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update PLDs to match the port layout:
Front (left to right):
C0, A1, A0
Left side:
C1
Also enable the usb 3.1 device.
BUG=b:264960828
TEST=USB2 and USB3 ports are peered correctly in the kernel:
Before:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6
After:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port2
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6
(Ports 5 and 6 are not used on boxy but are peered by default)
Change-Id: I1563d9eaa27353c8c97225a0a6ecc238e9275ce2
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
BUG=b:264960828
TEST=USB2 and USB3 ports are peered correctly in the kernel:
Before:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port5
After:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4
Change-Id: I5fe8066e361da62b747464b2ec09bcc6e7dda0fe
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77867
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Update the dibbi ec.h so that it's correct for a chromebox. Remove
everything related to:
- Lid
- Battery
- Built-in keyboard
- AC connect/disconnect
- Mode changes
BUG=b:294963793
TEST=Boot dibbi and check the APCI tables no longer contain lid and PS/2
keyboard devices.
Change-Id: Idfa5adcec308d68555d292fddc1db43c9a64d649
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77863
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Dibbi variants are chromeboxes, so they need different settings in ec.h.
Add a new dibbi baseboard ec.h and use it for dibbi variants. For now
it's identical to the dedede baseboard ec.h. It will be updated in the
following CL.
BUG=b:294963793
TEST=With the following CL, boot dibbi and check the APCI tables no
longer contain lid and PS/2 keyboard devices.
Change-Id: I4075041ab8f02026623d1a26a555bee5eb09e77b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77782
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
|
|
Add FW_CONFIG probe for absent FIVR bypass mode on peezer.
BUG=b:296982082
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: I0b2053b2d732fd9462686ed7b0c9225539b28fb2
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77396
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:297276380
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot
chromeos-bootimage
Cq-Depend: chrome-internal:6373154
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
|
|
Enable bit 9 for 100M mode green LED blink.
Reference:
- RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration
BUG=b:293983804
TEST=emerge-dedede coreboot and verify LAN LED behavior
Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
This change are added fine-tuned USB2 PHY parameters to improve the
USB2 eye diagram result.
BUG=b:296493887
BRANCH=firmware-dedede-13606.B
TEST=Local build bios successfully.
And verified the USB2 eye diagram test result.
Change-Id: I915fe689883267901e8faba28632345d8c227c28
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add support for ACPI display brightness controls, so that panel
adjustment is available under Windows.
TEST=build/boot Win11 on google/magpie, verify panel brightness
controls available and functional.
Change-Id: I66daa6bbca15046994dff83bee6e7cf99aae0b33
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77271
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update DPTF thermal settings from thermal team suggestion:
1. Modify CPU passive policy to 95.
2. Modify TS0/TS1/TS2 passive policy to 90 for CPU.
3. Modify TS1 passtve policy watt to 6w.
4. Modify TS0/TS1/TS2 critical policy to 100.
BUG=b:294479707
TEST=Build and verify DPTF value by thermal team on Boxy system
Change-Id: Ic34e44f218ff980c54bf93841880fab5e21b3fca
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77108
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Generate RAM ID for CXMT CXDB4ABAM-ML
DRAM Part Name ID to assign
CXDB4ABAM-ML 1 (0001)
BUG=b:290154780
BRANCH=dedede
TEST=FW_NAME=boxy emerge-dedede coreboot chromeos-bootimage
Change-Id: Ide44acf6bb8e5d5023c76d9e5e48ef113f7c6ec6
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76825
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Add ramstage.c in Makefile.inc and update boxy power limits in
Boxy ramstage.c.
BUG=b:290293153
TEST=emerge-dedede coreboot and check psys and PLx value on boxy
Change-Id: I4257dab358f066ebd13b6f251e8a5258a72fbd39
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76877
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the mainboard directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
BUG=b:279097356
TEST=On dibbi:
- flash OS 15449.0.0 (where suspend is broken due to b:274531972)
- run `suspend_stress_test --count=1 --suspend_max=30 --suspend_min=28`
- check the AP wakes up immediately when the EC detects a sleep hang
Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76938
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Add PLx from JSL PDG(ID: 613095) in boxy devicetree.
BUG=b:290293153
TEST=emerge-dedede coreboot and read correct value on boxy CPU log:
CPU TDP = 6 Watts, CPU PL4 = 60 Watts
Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Add the new memory support:
Samsung K4U6E3S4AB-MGCL
BUG=b:294151054
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run ./util/spd_tools/lp4x/gen_part_id.go JSL lp4x \
src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
Change-Id: Ief9bbf11fc05c8155f1da7188926a29dbbfbe488
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76542
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for Samsung K4U6E3S4AB-MGCL.
BUG=b:293240969
TEST=emerge-dedede coreboot
Change-Id: I92a1f2110e74b5d25572e0e86e04b5b32112c1f5
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. H54G56CYRBX247
2. H9HCNNNCPMMLXR-NEE
3. MT53E1G32D2NP-046 WT:B
4. K4UBE3D4AB-MGCL
5. K4UBE3D4AA-MGCR
BUG=b:290811418
BRANCH=dedede
TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage
Change-Id: Ib7f23dc3604fe1869772d92c9d7b8cc32ed9bbb9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Mapping to the fw_config of AUDIO_AMP in dedede,
and set new AUDIO_AMP configuration of ALC5650 as value 4.
BUG=b:284060672
BRANCH=dedede
TEST=build pass
Change-Id: Ic3dccd09d3ba1619cce2ac0d5f123badbeeaccdc
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:290876132
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Change-Id: Id5e0ba7a4ca57e311465ba8e74105f5ee7b8ee8a
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76435
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
- remove usb2_ports[5] since taranza doesn't have PL2303.
- add usb2_ports[6] and usb3_ports[1] for Type-A Port A4.
BUG=b:288094807, b:278167978
TEST=emerge-dedede coreboot chromeos-bootimage
verified all the USB port works
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7b411c21271497ba386143140aa8cfbb17a1a111
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76186
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The taranza removed the APW8738BQBI and "disable_external_bypass_vr" should be set to "1" to disable.
BUG=b:288978340
TEST=emerge-dedede coreboot
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I0a849fbfacba1d200c969c66bb058863d7ab3085
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Add ramstage.c in Makefile.inc and update Dibbi power limits in
Dibbi ramstage.c.
BUG=b:281479111
TEST=emerge-dedede coreboot and check psys and PLx value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75681
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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With newer dedede design, it's required to config corresponding
psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kinds of
adapter.
BUG=b:281479111
TEST=emerge-dedede coreboot and check correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: I583c930379233322c41027805369f81d02000ee7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75680
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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1.Add Codec ALC5650 setings for drivers/i2c/generic
2.Add option value '3' to AUDIO_CODEC_SOURCE for SSFC
BUG=b:284060672
BRANCH=master
TEST=emerge-dedede coreboot chromeos-ec chromeos-bootimage
Confirm the device is existed on system.
Change-Id: I39703a950620c90aa3740b7313b7d32cc68eede4
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75918
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
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Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.
BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Super Ni <super.ni@intel.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Boxy audio codec chip uses ALC5682I-VD, not ALC5682I-VS.
It needs to modify codec HID to "10EC5682" in coreboot to fix audio no
output sound issue.
BUG=b:286970886
BRANCH=dedede
TEST=confirm audio soundcard can be list by command "aplay -l"
Change-Id: Icd69a9d757ba817b586a703a17375682db684224
Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
The memory parts being added are:
1. K4U6E3S4AB-MGCL
2. K4UBE3D4AB-MGCL
BUG=b:285504022
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I87a4dcdb6196c3ca7bed4b5c1bc654297339c16d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75605
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Incorrect filename "MakeFile.inc" cause gpio.c can not be complied.
Rename to "Makefile.inc" and confirm gpio.c can load correctly.
BUG=b:281620454
BRANCH=dedede
TEST=build and confirm gpio.c can be loaded
Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I39947c66de04695e5242ab1affc328894f34f9f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75520
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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copy from dibbi since taranza base on dibbi,this is only for first
initial configuration, will update the more setting afterward.
BUG=b:277664211
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
BUG=b:277664211
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I6bbb67ccdd8ebc21719921d00320907f8dbb285f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74933
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The boxy removed the APW8738BQBI-TRG and
"disable_external_bypass_vr" should be set to "1" to disable
BUG=b:271407334
TEST=emerge-dedede coreboot
Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: Ic6667e93de41e84f67363ab7554fe755fe50684a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74889
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create overridetree and GPIO config based on latest schematic:
1. Update PCIe ports
2. Update USB ports
3. Remove unused I2Cs
4. Remove unused peripherals (SD card, eDP, speakers)
5. Add LAN
6. Thermal policy for updated temp sensors
BUG=b:277529068
BRANCH=dedede
TEST=build
Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I5a155ebca50dbd5bdb046713ebabbee395361273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74626
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Add all SOF chip drivers to baseboard and use FW_CONFIG to determine
the correct option, to ensure the correct audio config is passed to the
SOF OS drivers.
TEST=build, boot Windows on several dedede variants, verify audio
functional under Windows using coolstar's SOF drivers.
Change-Id: I9452b11af614d8727aa8dd448e37f7a06faa450d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74818
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Add boxy supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
3. Micron MT53E512M32D1NP-046 WT:B
BUG=b:278983561
TEST=Use part_id_gen to generate related settings
Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I317f2b31774627706babdea10776af05ab692d1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Create the boxy variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:277529068
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BOXY
Change-ID: Ief22eb000421c23abf6de3f99eb860bdae1e7919
Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add boten supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K4U6E3S4AB-MGCL
BUG=b:278138388
TEST=Use part_id_gen to generate related settings
Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I5f910393847c6494f77c009cb11f50b31bebffb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add G2touch touchscreen support for kracko.
BOE NV116WHM-T04 V8.0 with G7500 touch panel sensor IC
BUG=b:277852921
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot & test on DUT
Change-Id: Ic065d5dc2900c6ccfee09031f7a80cefc391f5dd
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74307
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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