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Configure the I2C bus high and low times for port0,2 and 4 I2C buses.
BUG=b:176519792
TEST=Measured the I2C bus frequency lower than 400 KHz.
Change-Id: Ieed038c93f0972c06cb3fa311742dd22ac2e875d
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Follow Goodix datasheet (GT7375 Programming Guide_Rev.0.1.pdf and
GT7375P Programming Guide_Rev.0.6.pdf) to tune touchscreen power sequence.
Increase reset_delay_ms from 120ms to 180ms.
BUG=b:176511605
BRANCH=dedede
TEST=Build and boot Madoo to OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iae35e4da31a3c3afd24c7daf81a5a3e762acd3b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:168783630
TEST=Measured the I2C bus frequency reduce to 387 KHz.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I37403dd3ac3c9320398207d2111e1ddb73d6a130
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Config I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
These tuning value is applied from touchpad as a base line,
and EE measured touchscreen/audio runs at 399/396.7kHz after tuning.
BUG=b:173709409
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz
Change-Id: I970d69e6361d7cf6fcfc4e5b0b3c5fbfa885367c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:173709409
BRANCH=dedede
TEST=EE measured result is 390.8kHZ
Change-Id: I7a6475fd29d4c9f8efa78a42a112b5565511b939
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update galtic device tree override to match schematics.
BUG=b:170913840
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
H9HCNNNCPMMLXR-NEE
BUG=None
TEST=Build the storo board.
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ifd935865927bb9fccf95eb4924ca6986d0c19442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update devicetree and gpio driving of boten that enable stylus
PEN detect signal is not dual-routed on Boten. Since the gpio_keys kernel
driver expects the pad to be owned by GPIO controller (i.e. configured for
GPIO IRQ), it cannot be configured for ACPI (i.e. SCI).
Thus, this change updates the GPIO configuration for GPP_C12 to
PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to
use WAKEUP_ROUTE_GPIO_IRQ. Additionally, the signal is marked as active
low in the device tree entry to indicate to the kernel driver that the signal
is inverted.
Not dual routing the signal results in wake source not being added to
eventlog when pen removal results in wake from S0ix.
BUG=b:160752604
BRANCH=dedede
TEST=Build and check behavior is expected.
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Change-Id: I74a17088da64c22ef1c74d201c80274fc65a44c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Falling back to default values for Imon slope and offset for Drawcia
This is as per recommendation from ODM based on calibration
This reverts commit 2ac88f2347352c5dff0af18d5130dbdd6f032930.
BUG=b:175629526
BRANCH=dedede
TEST=Debug FSP confirms that values are reverted to default
Change-Id: I605acdcd0de2c5dfc28af2aea8cefc6b629c0925
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48737
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for gpio driver for galtic
BUG=b:170913840
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I01bb95545705efab1a2adf1582b6293fd89e6420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48684
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable Acoustic noise mitigation for madoo and set slew rate to 1/8
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:173765599
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I968d8d43016e3569835b0a777335fa1d5c135f87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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galtic memory table as follow:
value Vendor Part number
0x00 MICRON MT53E512M32D2NP-046 WT:E
0x00 HYNIX H9HCNNNBKMMLXR-NEE
0x01 MICRON MT53E1G32D2NP-046 WT:A
0x02 HYNIX H9HCNNNCPMMLXR-NEE
BUG=b:170913840
BRANCH=none
TEST=emerge-dedede coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30b8fe3f14e1af7bb5760530477f9311c6a4ee62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add wifi sar for magolor and maglia:
Using tablet mode of fw config to decide to load custom wifi sar or not.
same wifi sar value for magolor and maglia (shared firmware)
BUG=b:173001370, b:173001251
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Cq-Depend: chrome-internal:3453724
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I44ab68c9ee5deced90d3858161571ab4b39b4c8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48448
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds memory part used by variant sasuke to
mem_part_used.txt and generates DRAM ID allocated to the part.
BUG=b:172104731
Change-Id: Ie8d66261cb5b4493afb1c677839f807bca994af5
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48451
Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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AP_PEN_DET_ODL isolated by a diode and need to pull up internally.
BUG=b:160752604
BRANCH=dedede
TEST=Build and confirm waveform by google EE parter.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48294
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Elan and Synaptics touchpad settings.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add HDA,speaker codec and speaker amp settings.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create the storo variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174284884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_STORO
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I5ad41e0b2bc95b44733a2ad3c543267f3f56f9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Enable Acoustic noise mitigation for drawcia and set slew rate to 1/4
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:162192346
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.
Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Default VBT supports only integrated Display port. Drawman supports a
HDMI port and hence support a separate VBT for Drawman.
BUG=b:161190931
BRANCH=dedede
TEST=Build and boot to OS in Drawlat and Drawman.
Cq-Depend: TBD
Change-Id: I8895cc67d87428eddb31328f1e3a90c346b54533
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Add daughter-board ports bit field and mask in devicetree.
BUG=b:161190931
BRANCH=dedede
TEST=Build and boot to OS in drawlat & drawman.
Change-Id: Ibbd86fc8c3e44a7d1703b8ce75c48881226545c9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Config HID-I2C device to level trigger.
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:171546871
TEST=emerge-dedede coreboot
Change-Id: If8be25f591715765a99920b79482c862b1cc7079
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Updating Imon slope and offset values as per recommendation of
ODM based on calibaration.
Updating Imon slope to 1.0 and offset to 1.4
BUG=b:167294777
BRANCH=dedede
TEST=Boot dedede platform and confirm values in FSP.
Change-Id: I3eb32218040163f0abef9b8dd4c52efb16289fe7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vinay Kumar <vinay.kumar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Create the sasuke variant of the waddledoo reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:172104731
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_SASUKE
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I29405d63fd266224807e535c3f86a2ad5ab8cdf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Create the galtic variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:170913840
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_GALTIC
Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47900
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC)
activation.
BUG=b:171531244
TEST=build and verify by thermal team
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47691
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Elan and Goodix touchscreen settings.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Ib2acd31a8076533c3b927d37127e7d27bac0bb57
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create the lantis variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:171546871
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_LANTIS
Change-Id: Ie3d15a687b870afc7d8bbeb6b5cab0792650da31
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=emerge-dedede coreboot
Change-Id: I9d8fa57ae0f554896a4a0722e3e89567676382d4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable USB2 port 5 for user facing camera.
Enable USB2 port 6 for world facing camera.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Iecb7787d46eab7096dec9f838a16da101105e09a
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Disable I2C port 3 for metaknight
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Ic4a056d53a8c8abd04a9b786428da0986a255276
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update Power Limit2 (PL2) minimum value to the same as maximum value
for magolor board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.
BUG=b:168353037
BRANCH=None
TEST=Build and test on magolor board
Change-Id: I74e960de506d366cba2c8aefb23f9e69337fd163
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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LTE module used in boten has a specific power on/off sequence.
GPIOs related to power sequnce are:
* GPP_A10 - LTE_PWR_OFF_R_ODL
* GPP_H17 - LTE_RESET_R_ODL
1. Power on: GPP_A10 -> 20ms -> GPP_H17
2. Power off: GPP_H17 -> 10ms -> GPP_A10
3. Warm reset: Power off -> 500ms -> Power on
Configure the GPIOs based on these requirements.
BUG=b:163100335
TEST=Build and boot Boten to OS. Ensure that the LTE module power
sequence requirements are met.
Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This support is required to power off certain components that exist only
in certain variants.
BUG=None
TEST=Build and boot Boten to OS.
Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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EEPROM in the camera module does not require any specific power
resources. This will ensure that no unnecessary resources are turned on
while accessing the camera EEPROM.
BUG=b:167938257
TEST=Build and boot to OS in Drawlat. Ensure that the camera EEPROM is
listed in the output of i2cdetect.
Change-Id: Iece9b3f657bf94a21cc08bf1745353575858f9b2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Handle AC connect and disconnect notifications from Embedded Controller
(EC) and wake from S3/S0ix.
BUG=b:172266344
TEST=Build and Boot to OS in Drawlat. Ensure that the system wakes up
from suspend on AC connect and disconnect on both the TypeC ports.
276 | 2020-11-04 12:21:29 | S0ix Enter
277 | 2020-11-04 12:21:40 | S0ix Exit
278 | 2020-11-04 12:21:40 | EC Event | AC Disconnected
279 | 2020-11-04 12:21:57 | S0ix Enter
280 | 2020-11-04 12:22:03 | S0ix Exit
281 | 2020-11-04 12:22:03 | EC Event | AC Connected
282 | 2020-11-04 12:22:35 | S0ix Enter
283 | 2020-11-04 12:22:47 | S0ix Exit
284 | 2020-11-04 12:22:47 | EC Event | AC Disconnected
285 | 2020-11-04 12:23:08 | S0ix Enter
286 | 2020-11-04 12:23:16 | S0ix Exit
287 | 2020-11-04 12:23:16 | EC Event | AC Connected
Change-Id: I7fa4ac0096548fd63af86e9f56c4c1ee25491399
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Update Power Limit2 (PL2) minimum value to the same as maximum value for
dedede variants (baseboard and drawcia). Currently, variants like boten,
waddledee, waddledoo, metaknight and wheelie uses the DTT entries from
baseboard devicetree since there is no override present for these variants.
So, these variants will also reflect this change of PL1 minimum value.
For madoo variant, PL2 minimum value already set the same as PL2 maximum
value. DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on drawcia system
Change-Id: I7ecf1ffcc7871192ebe18eb8c3c3fd3e1193721e
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47154
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
BUG=b:169813211
TEST=Build the metaknight board.
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Change-Id: I0d0d22f4790f66b5265803e4dcf01234a16b1993
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.
BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:168783630
TEST=Measured the I2C bus frequency reduce to 387 KHz.
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46613
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
To support mipi WFC.
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU
2. add IPU/VCM/NVM/CAM1 in devicetree
BUG=b:163879470, b:171258890, b:170936728, b:167938257
TEST=Build and boot to OS. Capture frames using camera app.
Change-Id: I96f2ef682dff851d7788c2b612765a92228ddf75
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44939
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the metaknight variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:169813211
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_METAKNIGHT
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Early JSL silicon hang while booting Linux with ISST enabled. The
malfunctioning silicon revisions have been used only for development
purposes and have been phased out. Thus, drop the ISST workaround.
Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Update PL1 max and min power values
BUG=None
BRANCH=None
TEST=build and verify on dralat system
Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Add devicetree and device ID for P-sensor
BUG=b:161217096
BRANCH=NONE
TEST=We can get the data from P-sensor if touch the SAR antenna.
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Update devicetree of boten that enable stylus
BUG=b:160752604
BRANCH=NONE
TEST=build bios and verify function for boten
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
The camera sensor component chosen for UFC and WFC have an address
conflict. Resolve it by enabling GPIO based I2C Multiplexer. Also
configure the GPIO that is used as select line.
BUG=b:169444894
TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers
are added for I2C devices multiplexed using I2C MUX under the
appropriate scope.
Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add tcc, critical, passive policy, and pl values from thermal team.
BUG=b:169215576
TEST=build and verify by thermal tool
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Refactor DPTF section of code under the baseboard devicetree
and overridetree. This makes override mechanism more simpler,
because not all the DPTF fields need to be overridden.
BUG=None
BRANCH=None
TEST=Built and tested on dedede system
Change-Id: I8e7cfe60c010ed4c07f9089325b289519e861f84
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Allow MRC training in SaGv low, mid and high frequencies.
TEST=Verify memory trains at low, mid and high SaGv point
through FSP debug logs enabled.
Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add trackpad, touchscreen, and usb port to devicetree
BUG=b:160664447
BRANCH=NONE
TEST=build bios and verify theirs function for boten
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This change drops maxsleep parameter from chip config and instead
hardcodes the deepest sleep state from which the WiFi device can wake
the system up from to SLP_TYP_S3. This is similar to how other device
drivers in coreboot report _PRW property in ACPI. It relieves the
users from adding another register attribute to devicetree since all
mainboards configure the same value. If this changes in the future, it
should be easy to bring the maxsleep config parameter back.
BUG=b:169802515
BRANCH=zork
Change-Id: I42131fced008da0d51f0f777b7f2d99deaf68827
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
If Cr50 is running old firmware version and hence does not ensure long
interrupt pulses, override the GPIO PM configuration.
BUG=None
TEST=Build and boot waddledee to OS. Ensure that any chip override
happens before FSP silicon parameter initialization. Ensure that the
suspend/resume sequence works fine. Ensure that the reboot sequence
works fine for 50 iterations.
Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Update TSR1 passive trip temperature
BUG=b:169691800
BRANCH=None
TEST=Built and tested on dedede system
Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
BUG=b:167472333
TEST=Build and boot dedede and observe the slope and offset values
getting updated in the fsp debug log
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I3ea32218040263f0abef9b9dd4c52efb16289fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45825
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
add tcc, critical, passive policy, and pl values from thermal team
BUG=b:168353037
TEST=build and verify by thermal tool
Change-Id: I887d494ff097a881d519a456f24578a278323051
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45453
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU
2. add IPU/VCM/NVM/CAM0 in devicetree
BUG=b:166527568
TEST= build and verify function by cam ap on DUT
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Ica6aa8ddc03a1dab5b548a759825dd3a4de3101f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45329
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Camera ACPI tables are generated at run-time for all variants of Dedede.
BUG=None
TEST=Build madoo variant.
Change-Id: Icb74c01a0a6dbc620466b64cd2b5652408ca41b9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
BUG=b:168847046
TEST=emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I16ed22aa5e270ad2d5c964764cc134b72941d4e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.
BRANCH=None
BUG=None
TEST=Built and tested on dedede board
Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
After adjustment on madoo
Touch Pad CLK: 381.9 KHz
Touch Screen CLK: 389.4 KHz
Audio CLK: 380.9 KHz
BUG=b:168565823
BRANCH=master
TEST=USE=build madoo and measure by scope with madoo.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: If281f9a8614e3e0ef20893b456f46e68ecb0631d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Add wifi sar for madoo.
Using tablet mode of fw config to decide to load custom wifi sar or not.
BUG=b:165105210
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ic6128b966c952cdc02a6359c14fa41f22265039a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
This change updates devicetree to enable SSDT generation for world
facing camera and user facing camera of Waddledoo. Also reverts DSDT
changes related to both the camera.
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: Ib7e875d297c04f35d4e980ff33d9a3767d2910ac
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
|
|
This enables the keyboard backlight feature in ACPI for madoo.
BUG=b:167943993
TEST=Verified 'kbd_backlight' shows up in the '/sys/class/leds '.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I11531699cb650b96becae5c1bec9f89c48b6bea0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
add the magolor touch screen ctrl devices:
1)elan 6915
2)elan 5012
3)raydium RM32680
BUG=b:166711761
BRANCH=None
TEST=build firmware and verify the touch functions on DUT
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Icd2963317e858f7d35c937e45cd6f3e556bbb953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45227
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add configuration for ALC5682 headphone jack and ALC1015 speaker
amplifier. Also turn on the HDA PCI device.
BUG=b:161667665
TEST=Build the boten board and verified the audio functionality.
Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W.
BRANCH=None
BUG=b:166656373
TEST=Built and tested on drawlat system
Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The debug statement to print WiFi SAR file can potentially have a NULL
pointer. Also the debug statement does not add much value. Hence remove the
debug statement.
BUG=b:165613510
TEST=Build and boot the drawcia board to OS.
Change-Id: I710240f5e965f523fb8ac55a67880e1cbf9abd48
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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drawman/drawlat/drawcia share the same coreboot, and only drawcia is convertible.
Use tablet mode of fw config to decide to load custom wifi sar or not.
BUG=b:165613510
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Change-Id: Ibcd498021e63d0a172c71c3d94b60b3a25973467
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable FW_CONFIG and add tablet mode field in devicetree
BUG=b:165613510
TEST=emerge-dedede coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I55e4c0d0b4aa2337c01773006d0b485fdcd91654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:162232776
TEST=Measured the I2C bus frequency as 389 KHz, high time as 870 ns and
low time as 1580 ns.
Change-Id: I67d2725a7fc8d83e3fa8a56cfa86540c4e6f0971
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45084
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:163743035
TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and
low time as 1680 ns.
Change-Id: I60a5f6814fb9818c724f6b6fe465ea49d0de0f97
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45083
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setting USBx_PORT_EMPTY is not a requirement anymore, since unset
devicetree settings default to 0 and the OC pin now only gets set when
the USB port is enabled (see CB:45112).
Thus, drop the setting from all devicetrees.
Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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BUG=b:155002684
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: I87d8575131e745dec818bc5864ca6b21ce0825af
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex).
BUG=b:160157545
TEST=run gen_part_id for volteer variants and verify that it changed
spd names to prepend the "lp4x-" to the filename..
Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:155002684
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: I89a4a5bbcd26b156a9660f80090bb5c953196b84
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add the configuration in device tree:
1. Add HDA,speaker codec and speaker amp setting
2. Add Elan and Goodix touchscreen setting
3. Add user facing camera usb setting
4 Add Synaptics and Elan Touchpad setting
5. Add WiFi configuration
BUG=None
BRANCH=None
TEST=build magolor firmware
Change-Id: Ifc562b4a05c8955d2aec105f2f429f926ad1e702
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44633
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add charger input current throttling for drawcia system
BUG=None
BRANCH=None
TEST=Built and tested on drawcia system
Change-Id: I34fdc23fcd84b5c27c2bada769f7a9049c2a56a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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IPU is required to be enabled for platform supporting MIPI camera.
IPU is by default disabled in devicetree for all variants. Enable
IPU for Waddledoo and Waddledee supporting MIPI camera.
BUG=None
BRANCH=None
TEST=IPU is enabled for platforms and enumerates in lspci.
Change-Id: Ia3cf06d78be4301c68bfa8b1118ddff231d24a66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44271
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure TRACKPAD_INT_ODL pad reset config to DEEP and
map PMC_GPE_DW to PMC_GPP values.
TEST=System should wake from S3 via trackpad
Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
And also remove the deprecated by cl#43989
https://review.coreboot.org/c/coreboot/+/43989
BUG=None
TEST=Build the magolor board
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I3348b7fbeff038b85e7d3c9137517e05a35bf3dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44408
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the SLP_Sx assertion width and power cycle duration
for the dedede platforms.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
reset on waddledoo.
Change-Id: I7079cbd564288b5d5b69e07661434439365063d3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia
system. Add information on sensors, power limits and tcc_offset for DTT
based thermal control.
BRANCH=None
BUG=b:161993459
TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Use tabs instead of eight (sometimes less) spaces.
Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Observed thermal shutdown initiated by DPTF due to CPU temperature
reaching critical temperature trip value. During stress testing with
heavy workload like WebGL Aquarium, sometime CPU temperature spikes
till 99 degree Celsius and DPTF initiates system shutdown. This
updates CPU critical temperature trip value to 105 degree Celsius
to avoid system shutdown.
BUG=b:161993459
BRANCH=None
TEST=Built and tested on dedede system
Change-Id: If15a873a997aa80f20940f27bbafd4498908c091
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44054
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add RTL8822CE support for Madoo.
BUG=b:162390420
BRANCH=None
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage, build successful
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I6e471be2b2856977e6f728d5a2ca78942725bea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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1. Add Elan touchpad support.
2. Follow schematic to disable I2C1 and I2C3.
BUG=b:160869188,b:161407664
BRANCH=NONE
TEST=emerge-dedede coreboot chromeos-bootimage", build successful
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I154a1ff2597968d200d1d0693718f90cd2744616
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Add Goodix touchscreen support.
BUG=b:160868197
BRANCH=None
TEST=emerge-dedede coreboot chromeos-bootimage", build successful
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I9bf27d69d0895cb4ea8620a6da49e98d25e05c23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44012
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add overridetree info for the touchscreen.
BUG=b:160129126
TEST=cros flash-ap -b dedede
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I55fc0749b824a0bf4b615d02bd8bc39bcdd589e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
BUG=None
TEST=Build the magalor board.
Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
BUG=b:161215903
BRANCH=NONE
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib61af2399541c4caf4a310a34e778e0ba1cbd3ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43802
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select the drivers for ALC5682 codec and MX98360A spk amp
BUG=b:161407664
BRANCH=NONE
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibe3d878b1058bfae4143d96be854884e61394ad5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Follow schematic to modify USB port setting and clean up I2C clock tuning.
USB2 [0]: USB Type C Port 0
USB2 [1]: USB Type C Port 1
USB2 [2]: None
USB2 [3]: USB Type A Port 1
USB2 [4]: None
USB2 [5]: Camera
USB2 [6]: None
USB2 [7]: WLAN module - BlueTooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: USB Type C Port 1 (Sub/B side)
USB3 [2]: None
USB3 [3]: USB Type A Port 1
USB3 [4]: None
USB3 [5]: None
BUG=b:161407664
BRANCH=NONE
TEST=Build the coreboot image on madoo board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia73593f52adee3806e725127891f084a08bf1360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43750
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow schematic to modify some GPIO pins.
GPP_D12 - NC Pin
GPP_D13 - NC Pin
GPP_D14 - NC Pin
GPP_D15 - NC Pin
GPP_E0 - NC Pin
GPP_E2 - NC Pin
GPP_H6 - NC Pin
GPP_H7 - NC Pin
GPP_S02 - NC Pin
GPP_S03 - NC Pin
BUG=b:161407664
BRANCH=NONE
TEST=Build the coreboot image on madoo board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I85aadfb0d020055eec921c7646c16ae6c95a606f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43745
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:161734657
TEST=Ensure that the discrete WiFi information is built into ACPI table.
Scope (\_SB.PCI0.RP01)
{
Device (WF00)
{
Name (_UID, 0x923ACF1C) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x43,
0x03
})
}
}
Change-Id: I9a9259e167fc213291b89e151729553ec4649eaf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43769
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MRC automatically detects the DDR type and sets Rcomp resistor
and target values for JSL and does not require explicit programming.
Change-Id: Ia130765e2cb91d6a39ad00ebbab20e7e87fa42d1
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
