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path: root/src/mainboard/google/dedede/variants/waddledoo
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2020-11-13mb/google/dedede: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=emerge-dedede coreboot Change-Id: I9d8fa57ae0f554896a4a0722e3e89567676382d4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21mb/google/dedede: drop obsolete ISST workaroundMichael Niewöhner
Early JSL silicon hang while booting Linux with ISST enabled. The malfunctioning silicon revisions have been used only for development purposes and have been phased out. Thus, drop the ISST workaround. Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-16mb/google/dedede: Replace static Camera ACPI by driver for WDooPandya, Varshit B
This change updates devicetree to enable SSDT generation for world facing camera and user facing camera of Waddledoo. Also reverts DSDT changes related to both the camera. Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Change-Id: Ib7e875d297c04f35d4e980ff33d9a3767d2910ac Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-08-28util: rename lp4x spds to include "lp4x-" in nameNick Vaccaro
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex). BUG=b:160157545 TEST=run gen_part_id for volteer variants and verify that it changed spd names to prepend the "lp4x-" to the filename.. Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21mb/google/dedede: Enable IPU for Wdoo and Wdee variantsMaulik V Vaghela
IPU is required to be enabled for platform supporting MIPI camera. IPU is by default disabled in devicetree for all variants. Enable IPU for Waddledoo and Waddledee supporting MIPI camera. BUG=None BRANCH=None TEST=IPU is enabled for platforms and enumerates in lspci. Change-Id: Ia3cf06d78be4301c68bfa8b1118ddff231d24a66 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44271 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/dedede/var/waddledoo: Configure stop delay for SiS TSKarthikeyan Ramasubramanian
Reset the Touchscreen (TS) and disable the stop GPIO (report switch) at the same time. Add a delay of 100 ms after disabling the stop GPIO. This will ensure the required delay is inserted for both reset and stop disable GPIOs simultaneously. BUG=b:152936541 TEST=Build and boot the waddledoo mainboard. Ensure that the SiS Touchscreen is functional. Change-Id: Icbfb5e07a28ab72b1ff696ad1183a6c2173dcaac Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43453 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18mb/google/dedede: Convert static DPTF ASL into devicetree entriesTim Wawrzynczak
Since there is now a mechanism to generate DPTF ACPI tables and methods at runtime, dedede should switch to using that instead of raw ASL files. This patch converts the existing .asl files into devicetree entries. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24jasperlake: enable DPTF functionality for dededeSumeet R Pawnikar
Enable DPTF functionality on jasperlake based dedede platform BRANCH=None BUG=None TEST=Built for dedede system Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/dedede: Re-configure the USB ACPI objectsKarthikeyan Ramasubramanian
In waddledee and waddledoo, discrete & integrated BT signals are routed to different USB ports. In all the other variant boards, discrete & integrated BT signals are routed to the same USB port (port 8 - index 7). Re-configure the USB devices accordingly. Also device configuration in override tree are applied only if there is a matching device in base devicetree. So configure all the USB devices in base devicetree and turn them off. BUG=b:154064148 TEST=Ensure that the SSDT contains the ACPI objects for enabled USB devices. Change-Id: I1b8bf7f4db1d2661f310bf4874428a6d1de222c6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42554 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10mb/google/dedede/variants/waddledoo: Adjust I2Cs CLK to meet specJohn Su
After adjustment on waddledoo Touch Pad CLK: 392.9 KHz Touch Screen CLK: 387.4 KHz Audio CLK: 350.9 KHz BUG=b:151302522 BRANCH=master TEST=emerge-dedede coreboot chromeos-bootimage measure by scope with waddledoo. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iec02a751f1effdbefbb2969db2fd57f27ecdd033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42187 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede: Switch to using auto-generated SPDsFurquan Shaikh
This change switches dedede and family to using auto-generated SPDs obtained using gen_spd.go and gen_part_id.go. Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41881 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledoo and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:E Byte# Current New Explanation 4 0x15 0x16 This part has only 1 die. Hence, density per die is 16Gb. 6 0x90 0x04 1 die in package and 2 channels per die. 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Waddledoo started assigning DRAM part IDs from 1. So, this change fills in Nanya part as ID 0 (though it is currently unused). Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-28mb/google/dedede: Enable Intel Speed Shift TechnologyKarthikeyan Ramasubramanian
Enable Intel Speed Shift Technology (ISST) by default. Disable ISST in waddledee and waddledoo variants on early phases. BUG=b:151281860 TEST=Build and boot the mainboard. Ensure that cpufreq driver to configure P-states is enabled in kernel on boards where board version is provisioned. Change-Id: Id65d7981501c2f282e564bfc140f8d499d5713e8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-05-18mb/google/dedede: update SPD name based on DRAM characteristicMarco Chen
The index of DRAM_STRAPS indicates to a specific DRAM characteristic instead of a DRAM part number therefore update the existing DRAM SPD binary to the naming by DRAM characteristic. BUG=b:152019429 BRANCH=None TEST=build the image and verify that coreboot log shows the correct SPD info Change-Id: I8ffcf156f37a465209740c5e2a34effb5f1f5d5c Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13mb/google/dedede/variants/waddledoo: Modify ELAN touchscreen slave addressIan Feng
Modify ELAN EKTH6918 USI touchscreen slave address to 0x10. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I999967b0f37c82ff7811e3b6117baab795a11195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/google/dedede: Enable USB port for camera supportIan Feng
Support USB Chicony user facing camera. BUG=b:155109736 BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using user facing camera. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I7580a58086977e239dca49c1def4f03583831662 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mb/google/dedede: Remove pad termination for RAM_STRAP_4Karthikeyan Ramasubramanian
The stuffed resistor straps are weaker compared to the internal pull-up. This can cause the GPIO to read '1' always. Remove the internal pull-up. Also read the GPIO only on the boards where the board version is populated. BUG=b:154301008 TEST=Build and boot the mainboard. Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01mb/google/dedede: Enable camera support for waddledooPandya, Varshit B
BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: I51dcf96a82535fc1e0b9247fd52af919885575e5 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-20mb/google/dedede: remove samsung-K4U6E3S4AA-MGCL.spd.hexMarco Chen
The samsung-K4U6E3S4AA-MGCL.spd.hex is not used and planed by anyone yet. On the other hand, the spd content is not correct based on JSL spec as well. BUG=b:153426401 TEST=build waddledoo and waddledee successfully. Change-Id: If71e3ef2e3385378633549bf8709a1cd6ecc0dd3 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-14mb/google/dedede: Enable ELAN touchscreen for WaddledooDtrain Hsu
Add ELAN EKTH6918 USI touchscreen support. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I030c7d7e76a9705be06fe907c4ac279e247cb163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-14mb/google/dedede: Enable SIS touchscreen for WaddledooDtrain Hsu
Add SiS9813 USI touchscreen support. BUG=b:152936541 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Id04c46c763fdf68418bf2e97be4c8bb6bb73c749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40250 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-01soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoCAamir Bohra
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board. Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-20mb/google/dedede Add Audio support for waddledooAamir Bohra
1. Configure Audio GPIOs. 2. Set i2c4 configuration. 3. Update PCH HDA configuration TEST=Verify codecs gets listed with aplay -l command. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-14mb/google/dedede: Configure WLANKarthikeyan Ramasubramanian
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-12mb/google/dedede: Enable trackpad supportPandya, Varshit B
1. Configure trackpad interrupt GPIO. 2. Set i2c0 configuration. 3. Add trackpad ACPI support. TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz on trackpad operation. Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-11mb/google/dedede: Add SPD hex file for Samsung memory partMeera Ravindranath
BUG=b:150154457 BRANCH=none TEST=Build dedede, flash and boot to kernel. Change-Id: I7248861efd1edd5a0df0e17d39a47c168cab100e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39348 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03mb/google/dedede: Add memory initialization support for dededeMeera Ravindranath
Update memory parameters based on memory type supported by dedede 1. Update dq/dqs mappings 2. Update spd data for Micron Memory 3. Add SPD data binary files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST=Build dedede, flash and boot to kernel. Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24mb/google/dedede: Add waddledoo variantKarthikeyan Ramasubramanian
Add initial support for waddledoo board. BUG=None TEST=Build the mainboard and variant board. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-01 09:28:16 +0000