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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
BUG=None
TEST=Build the drawcia board.
Change-Id: Id05c0b2a87b64bfedc761949cbc8ad6cf7dd73a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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