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Correct GPIO settings as below reason:
1. GPP_G7 not being used but set to NF.
2. GPP_C22 and GPP_C23 is set to NC but internal pull down to 20K
BUG=b:177283756
BRANCH=dedede
TEST=emerge-dedede coreboot chromeos-bootimage and boot into emmc
Change-Id: Idf25674efa2336bde98c5abaff278484fd71ea8b
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Replace i2c driver for the SX9324 proximity detector device.
This is first draft settings, will modify it after fine tuning.
BUG=b:175932166
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm registers as except.
un-approach:
=> register address: 0x01 value: 0x00
approach:
=> register address: 0x01 value: 0x02
Change-Id: I0c8b5948266a07092799c6db556383fa08b924e6
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Correct GPIO settings as below reason:
1. GPP_D19/GPP_D20/GPP_D21 not being used but set to NF.
2. GPP_B7 should configure as WWAN SAR detect ODL, but set to NC
BUG=b:175932166
BRANCH=dedede
TEST=emerge-dedede coreboot chromeos-bootimage and boot into emmc
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Id7780d5332551ed3fd20ef14f8b5d31164f16385
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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LTE module is not expected to be powered off during warm reset. Hence
configure the LTE_PWR_OFF_ODL (GPP_A10) gpio pad reset configuration to
PWROK and set the TX state to 1.
BUG=b:163100335
BRANCH=dedede
TEST=Verified through the waveforms that power sequence is meeting the LTE module requirements.
Change-Id: I8676da6186559288aabe078b6158fc01075c7b41
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update ELAN i2c-hid touchscreen configuration
BUG=b:172517685
BRANCH=dedede
TEST=Verify touchscreen is working fine on botenflex
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Ia7c81fd0a772968ec32406f1e366a90481fc5ad8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:168783630
TEST=Measured the I2C bus frequency reduce to 387 KHz.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I37403dd3ac3c9320398207d2111e1ddb73d6a130
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update devicetree and gpio driving of boten that enable stylus
PEN detect signal is not dual-routed on Boten. Since the gpio_keys kernel
driver expects the pad to be owned by GPIO controller (i.e. configured for
GPIO IRQ), it cannot be configured for ACPI (i.e. SCI).
Thus, this change updates the GPIO configuration for GPP_C12 to
PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to
use WAKEUP_ROUTE_GPIO_IRQ. Additionally, the signal is marked as active
low in the device tree entry to indicate to the kernel driver that the signal
is inverted.
Not dual routing the signal results in wake source not being added to
eventlog when pen removal results in wake from S0ix.
BUG=b:160752604
BRANCH=dedede
TEST=Build and check behavior is expected.
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Change-Id: I74a17088da64c22ef1c74d201c80274fc65a44c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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AP_PEN_DET_ODL isolated by a diode and need to pull up internally.
BUG=b:160752604
BRANCH=dedede
TEST=Build and confirm waveform by google EE parter.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48294
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=emerge-dedede coreboot
Change-Id: I9d8fa57ae0f554896a4a0722e3e89567676382d4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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LTE module used in boten has a specific power on/off sequence.
GPIOs related to power sequnce are:
* GPP_A10 - LTE_PWR_OFF_R_ODL
* GPP_H17 - LTE_RESET_R_ODL
1. Power on: GPP_A10 -> 20ms -> GPP_H17
2. Power off: GPP_H17 -> 10ms -> GPP_A10
3. Warm reset: Power off -> 500ms -> Power on
Configure the GPIOs based on these requirements.
BUG=b:163100335
TEST=Build and boot Boten to OS. Ensure that the LTE module power
sequence requirements are met.
Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add devicetree and device ID for P-sensor
BUG=b:161217096
BRANCH=NONE
TEST=We can get the data from P-sensor if touch the SAR antenna.
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update devicetree of boten that enable stylus
BUG=b:160752604
BRANCH=NONE
TEST=build bios and verify function for boten
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add trackpad, touchscreen, and usb port to devicetree
BUG=b:160664447
BRANCH=NONE
TEST=build bios and verify theirs function for boten
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add configuration for ALC5682 headphone jack and ALC1015 speaker
amplifier. Also turn on the HDA PCI device.
BUG=b:161667665
TEST=Build the boten board and verified the audio functionality.
Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex).
BUG=b:160157545
TEST=run gen_part_id for volteer variants and verify that it changed
spd names to prepend the "lp4x-" to the filename..
Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust GPIO setting to match boten design
BUG=b:160741777
BRANCH=NONE
TEST=Add gpio.c for boten
Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com>
Change-Id: I4eafee608f657f8ec5a06caf6e99b08b3330512b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43277
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since there is now a mechanism to generate DPTF ACPI tables and methods
at runtime, dedede should switch to using that instead of raw ASL files.
This patch converts the existing .asl files into devicetree entries.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable DPTF functionality on jasperlake based dedede platform
BRANCH=None
BUG=None
TEST=Built for dedede system
Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial support for boten variant board.
BUG=b:158023819
BRANCH=None
TEST=build
Change-Id: I56fe901c6aec781fac217ab08f7583cc25788688
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
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