Age | Commit message (Collapse) | Author |
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Enable I2C ports that are used. Add GPIO configuration for the I2C
ports. Enable config items that are required for I2C HID & Generic devices.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I12e974530fb5f61fae5d12cadbb3f928e617d73a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Enable UART Port 2 as console UART and configure the concerned GPIOs.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn on the H1 device in the devicetree. Configure the concerned GPIOs
and enable the required config items.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I37972635454cd0d35608623e7be4110012ace658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38739
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:144768001
TEST=Build Test
Change-Id: Ibb94849a903e4d4364d817de8988a430cd717e4c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add stub implementation of smihandler.
BUG=b:144768001
TEST=Build test.
Change-Id: I7ab25888812bfb4578915e342b14355ccd15f5cc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add stubbed out GPIO configuration and perform GPIO initialization
during bootblock and ramstage.
BUG=b:144768001
TEST=Build Test
Change-Id: I1397b6a433e5046650f64f7eb9a84c51eb0c7441
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38278
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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