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To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the mainboard directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Realtek speaker amplifiers under auto mode operation have Absolute Max
Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker
amplifier and program the VCCIOSEL accordingly.
BUG=b:194120188
TEST=Build and boot to OS in Storo. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: Ibd3bc90bd0bbc9a35922b29e3d1e106321bc7a06
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56616
Reviewed-by: Evan Green <evgreen@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit ce79ceec86a38145b3a27aa4c78cf83a76cd51d0. This has
introduced a regression in mainboards using JSL SoC such that it
overrides the soft straps for all the GPIOs. This in turn has led to
some of the peripherals not working.
Change-Id: Ifea5d4d0f474873f8bf4818ec1986e534f455216
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56615
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Realtek speaker amplifiers under auto mode operation have Absolute Max
Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker
amplifier and program the VCCIOSEL accordingly.
BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: Ifa0b272c23bc70d9b0b23f9cc9222d875cd24921
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change switches dedede and family to using auto-generated SPDs
obtained using gen_spd.go and gen_part_id.go.
Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41881
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id0bb5266246dbd959c6497d7c411f908cc49318c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Update memory parameters based on memory type supported by dedede
1. Update dq/dqs mappings
2. Update spd data for Micron Memory
3. Add SPD data binary files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add helper functions to get board's sku_id and fw_config. Enable
EC_GOOGLE_CHROMEEC_BOARDID to get board_id. Add board's SKU ID and
OEM name into SMBIOS table.
BUG=b:144768001
TEST=Build Test.
Change-Id: Id1729e245accf5acc29307a22721362fb1ce0878
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38551
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Perform EC initialization in bootblock and ramstages. Add associated ACPI
configuration.
BUG=b:144768001
TEST=Build Test.
Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:144768001
TEST=Build Test
Change-Id: Ibb94849a903e4d4364d817de8988a430cd717e4c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add stub implementation of smihandler.
BUG=b:144768001
TEST=Build test.
Change-Id: I7ab25888812bfb4578915e342b14355ccd15f5cc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add stubbed out GPIO configuration and perform GPIO initialization
during bootblock and ramstage.
BUG=b:144768001
TEST=Build Test
Change-Id: I1397b6a433e5046650f64f7eb9a84c51eb0c7441
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38278
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add mainboard stubs for Dedede. More functionalities will be added later.
BUG=b:144768001
TEST=Build test.
Change-Id: I7e6cb8adaee7b6bb95e9a96f96466646a78bd0fc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38277
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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