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Currently thermal event support can not be disabled at board level.
Define and dependent code are placed in same file.
Move define of HAVE_THERM_EVENT_HANDLER to mainboard file.
Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27415
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for google/terra (Asus Chromebook C202SA/C300SA) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new terra variant
- Add code to the baseboard to handle terra's unique thermal management
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-terra-7287.154.B,
commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits:
- Keep code common to all Google Braswell boards in the baseboard,
and separate out the board-specific bits into the new cyan variant.
- Define the I2C ACPI devices such that they can be easily reused for
other variants.
- Switch the trackpad/touchscreen interrupts from edge to level,
for better performance/compatibility, as was done with all previous
Google boards.
- Add code to the baseboard to allow optional variant-specific
parameters to be used for both memory and silicon init.
- Remove superfluous includes, replace some hardcoded values with
variables, and correct typos/formatting errors.
Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Some trivial cleanup.
Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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TEST=Run DPTF
CQ-DEPEND=CL:12729
Original-Reviewed-on: https://chromium-review.googlesource.com/295478
Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifa58ad72105d377c00df577f0e16ff1148b70119
Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Reviewed-on: https://review.coreboot.org/12747
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Charger performance states table defines charger current limit for each
p state. Modify charger current control values for SANYO battery used
in Cyan.
BUG=None
BRANCH=None
TEST=System is charging battery, in shell window, issue command
"echo 0 > /sys/class/thermal/cooling_device4/cur_state",
"echo 1 > /sys/class/thermal/cooling_device4/cur_state",
"echo 2 > /sys/class/thermal/cooling_device4/cur_state",
"echo 3 > /sys/class/thermal/cooling_device4/cur_state", or
"echo 4 > /sys/class/thermal/cooling_device4/cur_state", will see EC
console show different charging current value.
Change-Id: Ie9bc78822a73de6bed338bfbcc5e9045653689dc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3a6162151d1f9c756a13d2afc17f6b9c18608efc
Original-Change-Id: I71e8247d057e4728eedcd5e8a275b64428290d09
Original-Signed-off-by: li feng <li1.feng@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285605
Original-Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: http://review.coreboot.org/11004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add initial files for the cyan board.
Matches chromium tree at 927026db
This board uses the Braswell FSP 1.1 image and does not build
without the FspUpdVpd.h file.
BRANCH=none
BUG=None
Test=Build and run on cyan
Change-Id: I935839be033c25e197e78fbee306104b4162a99a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10182
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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