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Initialize SPI bus 2 for TPM control.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Set VB2_CONTEXT_EC_TRUSTED in verstage_main.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Initialize SPI bus 1 for Chrome EC control.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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There is no support for SD card on Corsola reference board, so
we add a configuration to disable SD card initialization to
prevent setting GPIOs in a mistaken way.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Corsola the RAM code can be
read from ADC channel 2 and 3.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Raise little CPU to 2GHz at romstage.
TEST=check little core cpu frequency is 2GHz
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add VPROC12/VSRAM_PROC12 to adjust power for raising little
CPU frequency.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I59b4627220022a51a116716036a8ba0048039508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Configure Chromebook specific GPIOs, including EC_AP_INT,
EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add support for RTC and clkbuf.
TEST=boot to kernel and check log ok
BUG=b:202871018
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ia02a74f685feb2466c113a77cbfa3a7d8fedb595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Initialize SPM (System Power Management) in RAM stage.
This adds 55ms to the boot time.
TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I822417f7a679107760b202dd43fb79d1934940bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
TEST=boot kernel from eMMC ok
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.
TEST=boot kernel from eMMC and SDCard ok
BUG=b:202871018
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.
TEST=build pass
BUG=b:202871018
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add VMCH and VMC for providing power of SDCard.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I50fc87415086eb22ff35d157dba38cfd7594cc40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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1. Enable and setup USB drivers.
2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset
the hub via GPIO149.
TEST=boot kernel from USB ok
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Use regulator interface to use regulator more easily.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ied43cba51036c62a120df2afffeb63b5d73f012b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The 'corsola' reference design will include two implementations
with different BOM selections - 'krabby' and 'kingler'.
TEST=none
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iaf9c6af1a395030937a9a5c00e95d7246ddcb6eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add basic support for VCORE/VDRAM1/VDDQ of MT6366.
TEST=build pass
BUG=b:202871018
Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I22e30421560a32f4a9e15899e8150376b1414494
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add NOR-Flash drivers to pass verification of flash at verstage.
TEST=boot to romstage
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add mainboard folder and drivers for new reference board 'Corsola'.
TEST=build pass
BUG=b:200134633
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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