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path: root/src/mainboard/google/cherry/chromeos.c
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2022-03-29mb/google/cherry: support max98390 audio ampTrevor Wu
The Cherry follower projects may choose Max98390 for audio output so we have to add a new config CHERRY_USE_MAX98390. Also, the 'dojo' device is the first one to use it. BUG=b:204391159 BRANCH=cherry TEST=emerge-cherry coreboot TEST=Verify beep function through CLI in depthcharge successfully Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63083 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/cherry: Support audio codec RT1011Trevor Wu
Add GPIO "rt1011 reset" and i2c2 initialization for RT1011. Add CHERRY_USE_RT1011 and CHERRY_USE_RT1019 to Kconfig, so we can spearate code for the specific codec by config. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: I18939a2a2caae0444ce17f4712764647975121ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/57157 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16mb/google/cherry: Allow payloads to enable USB VBUSYu-Ping Wu
Configure GPIO DGI_D4 (AP_XHCI_INIT_DONE) as output, so that payloads (for example depthcharge) can assert it to notify EC to enable USB VBUS. BUG=b:193499785 TEST=emerge-cherry coreboot BRANCH=none Change-Id: I21b7b811b8138cb3f71efecb0a0a886905c65a9c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-06-17mb/google/cherry: fix GPIO polarity for TPM interruptRex-BC Chen
The GPIO_GSC_AP_INT itself is active low, but the payloads will create the IRQ using its eint driver, which is active high. BUG=b:188392736 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie39f3b9a5dbe15057ef3e96f6c99211949692003 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-26mb/google/cherry: Support audioTrevor Wu
Add GPIO "beep enable" for switching on and off. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: Iddb781e30fa90f05767cceeb83e623432540dcc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10mb/google/cherry: Configure TPMYidi Lin
Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10mb/google/cherry: Enable Chrome ECYidi Lin
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iab3549b5c4e7d845ddd284a0df3fb448e11fbdcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/53899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-07mb/google/cherry: configure GPIOsYu-Ping Wu
Configure Chromebook specific GPIOs, including EC_AP_INT, SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK. Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52924 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14mb/google/cherry: Add MediaTek MT8195 reference boardYidi Lin
TEST=boot from SPI-NOR and UART works fine. Change-Id: I279b3d2da8a30b38686005212f6c019a9a646874 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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