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2018-03-28soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-25soc/intel/skylake: Add LPC and SPI lock down config optionSubrata Banik
This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-10google/chell: remove non-existent touchscreenMatt DeVillier
Chell doesn't have a touchscreen, so remove the driver definition from devicetree. Leave the PCI device function 0 enabled since disabling results in the touchpad (function 1) being disabled as well. Change-Id: I32619b7618bc0cdd99fa54fdda9bf2b5c1bb79a4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-26mainboard/google/chell: Set TCC activation offset to 10 degree CSumeet Pawnikar
With the default TCC activation offset value as 0 and Tjmax temperature value as 100 degree C, Pcode firmware starts taking prochot action at 100 degree C [Tjmax-Offset]. But before Pcode firmware starts prochot action at 100 degree C, device is getting shutdown at 99 degree C due to DPTF critical CPU temperature. This patch sets TCC activation offset value to 10 degree C for thermal throttle action to prevent this kind of shutdown. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built, booted on skylake and verified target offset value. Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17921 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-28soc/intel/skylake: Add USB Port Over Current (OC) Pin programmingSubrata Banik
Program USB Overcurrent pins as per board schematics definition. BUG=none BRANCH=none TEST=Build and boot kunimitsu from USB device. Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-11soc/intel/skylake: move i2c voltage config to own variableAaron Durbin
In preparation of merging the lpss i2c config structures on apollolake and skylake move the i2c voltage variable to its own field. It makes refactoring things easier, and then there's no reason for a separate SoC specific i2c config structure. BUG=chrome-os-partner:58889 Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17347 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-08skylake/devicetree: Add PIRQ Routing programmingBarnali Sarkar
Program PIRQ Routing with correct values, as done by FSP, and also in 'soc/intel/skylake/romstage/pch.c' file. If not done, these values get overridden by "0" during PxRC -> PIRQ programming in ramstage, in 'soc/intel/skylake/lpc.c' file pch_pirq_init()function. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-07-28skylake/devicetree: Add LPC EC decode rangeSubrata Banik
Define LPC decode ranges for EC communication. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu to ensure no EC timeout error Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15898 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24google/chell: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified by comparing the generated ACPI code in the SSDT to what was in mainboard.asl and ensuring the contents are functionally equivalent. Change-Id: I4725bbe2d47178568e3024fe3bb48cc80ff861c3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09skylake: Move I2C bus configuration to separate structureDuncan Laurie
Move the existing I2C voltage configuration variable into a new structure that is equivalent, similar to how USB ports are configured. This is to make room for additional I2C configuration options like bus speed and whether to enable the bus in early boot which are coming in a subsequent commit. The affected mainboards are updated in this commit so it will build. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e Reviewed-on: https://review.coreboot.org/15104 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-12glados/chell: send an extra VR mailbox commandRizwan Qureshi
MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode has been updated since v76, and it requires an an extra VR mailbox command should be sent from coreboot to pcode. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low CQ-DEPEND=CL:329393 Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2 Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329480 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-01Skylake boards: Enabling HWP (hardware P state control)Subrata Banik
This patch provides config options to enable/disable Intel SST (Speed Shift Technology). BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: https://review.coreboot.org/13843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04skylake boards: disable ACPI PM TimerArchana Patni
These devicetree patches set the ACPI PM Disabled variable to 1. This will disable the ACPI PM timer and remove from FADT table. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319362 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22intel/skylake: PL2 override changespchandri
Override the default PL2 values with ones recommended by Intel. BUG=chrome-os-partner:49292 BRANCH=glados TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W MMIO 0x59A0[15] to find PL1 enable/disable = Disable MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W Here PL2 is set to 25W and PL1 is disabled. CQ-DEPEND=CL:321392 Change-Id: I338b1d4879ae1b5f760e3c1d16e379a2baa1c965 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa6a115227385bef44abfacf58af306c16ed478a Original-Change-Id: I3bfc50256c9bdd522c984b11faf2903d7c44c81f Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322454 Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/13071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Set FSP params for min assertion widths and serirqDuncan Laurie
- Enable serial irq configuration in FSP. - Set minimum assertion width values for FSP to configure. - Set I2C4 voltage to 1.8V. - Enable SaGv feature to dynamically train memory frequency. BUG=chrome-os-partner:47688 BRANCH=none TEST=build and boot on chell EVT Change-Id: If6955c9ee4f08d1ebc6e98e0ba0786073919856f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7403149299ec2c6c66c2066a5dd8294608e71409 Original-Change-Id: Ia182396ad4eb7a283e183fce7c50c98f6d2de57c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/321212 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13009 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Enable eMMC HS400 modeRyan Lin
Hynix eMMC can now run under HS400 mode. BUG=chrome-os-partner:47647 TEST=run consective boot 100 times on Chell EVT Hynix SKU, and MMC errors didn't happen. BRANCH=none Change-Id: Icb6fc03d0510d2c5aeb5b08ed7189e954ab39a72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9966c430a508a13cf1a617f485a48866bec161ca Original-Change-Id: I6bec88f5c2813131a693ddba5523a9d43b2ebd45 Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319627 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19google/chell: Enable FspSkipMpInit tokenBarnali Sarkar
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=none CQ-DEPEND=CL:319353 Change-Id: I22c1add182b299e2ad9d413bc13c5a5acc6a3179 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ccf89c9d1fe18b74c385e7d12a6aef5b63d7b243 Original-Change-Id: I53b754fd10a140588ad67d9292d9bc04a6d43677 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319194 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13000 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/chell: Add VR config settingsrobbie zhang
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due to a known issue (not able to hit S0ix) on glados. The VR settings will then need to be updated per the board VR design. BRANCH=none BUG=chrome-os-partner:48466 TEST=Build and booted chell Change-Id: Ieb014e2a0cee1cb02a1c095da273b5ac1a19ef5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcd47a2fb2b369a93d2992fa1c17c2ce91c0e948 Original-Change-Id: Iac197314702fe5897359afc1ad1636bbcdafa204 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317870 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/chell: Minor updates from EVT and FSP 1.8.0Duncan Laurie
- Add pullup on LPC address lines for leakage - Configure PCH_WP early so it gets set properly in VBNV - Disable SD card reader in favor of USB BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell EVT Change-Id: Ibac79c6cbef0515b1e8a513cfde5fee184e4c70a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ebd0c16a6009b74d3c6c36878c502fda9bb3020d Original-Change-Id: If2bc4eb546a1aab50d3688b6e92f8c38214c9cca Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317241 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12979 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18skylake boards: csme: add p2sb device and hecienabled devicetree variableArchana Patni
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0 (default) disables Heci1 and hides the device from OS. It internally uses the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb device in the devicetree which is necessary for hiding and unhiding the device. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for kunimitsu. CQ-DEPEND=CL:*238451 Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05 Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311913 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12977 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-03google/chell: Update mainboard for EVTDuncan Laurie
- Disable kepler device, it is removed and was not used on proto anyway. - Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM. - Disable HS400, this is breaking some devices on proto boards and is being disabled to reduce risk for EVT build. - Change Type-C USB2 port drive strength. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell proto Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180 Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313825 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11google/chell: Disable Deep S3Duncan Laurie
In order to wake from trackpad and wifi we cannot enable Deep S3. BUG=chrome-os-partner:46289 BRANCH=none TEST=wake from trackpad on chell Change-Id: Ieb2210d5d15b5f5d744a686c743df11e5d72558f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cbc74e13b754249869144df84ab2bb9b7e77119a Original-Change-Id: I84265197fb964e0594a4672a40fd3e2362e29ae1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311306 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12392 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11google/chell: Fix USB port assignment againDuncan Laurie
The net names are offset by 1. My board is not stable enough to really test all of these yet... BUG=chrome-os-partner:46289 BRANCH=none TEST=emerge-chell coreboot Change-Id: I65e17323f2819eca130c1bf0ccbc3ea0ec2f383f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 327194dcfcb3a5c9f431b1a2e26c230cb2b2a48b Original-Change-Id: I50e9ea091bb6e6a1da3a9434ae0fbf3f652fa354 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311113 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12389 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05google/chell: Fix USB port assignmentDuncan Laurie
The PCH pin names in the schematic were incorrectly labeled. BUG=chrome-os-partner:46289 BRANCH=none TEST=build and boot on chell Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/310061 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12324 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-27intel/skylake: Clean up USB configuration in devicetreeDuncan Laurie
Instead of having many different arrays for USB configuration, with each array containing one bit of information, have one array containing all the information for each port. This way we can put the basic tuning parameters into a structure and then define structures for the basic supported configurations. The existing port definitions are taken from the Skylake HSIO tuning guide. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados, verify USB functionality in all ports. Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506 Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/306734 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12163 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/chell: Add new mainboard for chellDuncan Laurie
This is based on glados with minor changes: - updated GPIOs based on schematic - add _PRW for trackpad wake now that it is on a new GPIO - add SPD for new memory config - disable ALS BUG=chrome-os-partner:46289 BRANCH=none TEST=emerge-chell coreboot Change-Id: Id5746bf2b5b26000fcc3f029b901bfe29b788dac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c5ebe98cf599ba80aac5e9ef238b7996789a819 Original-Change-Id: I75efda64a50b0e6e4a5c9008ce05d76c1e605b0c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304927 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12151 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/chell: copy glados to chellDuncan Laurie
Only change is renaming all occurrences of glados to chell, keeping capitalization. Change-Id: I8b1a3efd03d415f27c8872827f8687babbc539f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12150 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 18:51:01 +0000