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Adjust audio codec i2c timing to 399 kHz.
BUG=b:262959586
TEST=FW_NAME=gladios emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I2f621e3af39fb40ab270c9de35d51dd43147b8f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add wifi sar table for kuldax
BUG=b:248367859
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage
Change-Id: I5ade590c739aae391e47e8bb66ee03c086e8d56e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71270
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:252966799
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Change-Id: I15c3eea6ebb7f104bce0ba8cb544ecde7f488343
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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On Marasov, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on Marasov.
TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.
Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0
After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1
Change-Id: I4b65b8909c41b06852fe7771375029bd2e76e111
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71263
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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For marasov, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.
TEST=Boot to OS on Marasov UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.
Change-Id: I278e5d403ef9515e538a527f43949e505d750bb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71261
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
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Kano didn't use SSFC in mass production, however
Zydron needs SSFC for 2rd source mipi instead of fw_config.
BUG=b:262939431
TEST=Boot to OS and check functional with ov2740/hi556 camera.
Change-Id: Idb2a35d67af0b5a7dedc66b0f7eccd8a3b4612d1
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Use get_wifi_sar_fw_config_filename to remove the duplicate code.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I04176fee373e534d42c72506df73a092ad55e65b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Use get_wifi_sar_fw_config_filename to remove the duplicate code.
WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist
id has the same outcome.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib7a764d8cc3160c26abad9c1757812b955bef066
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Use get_wifi_sar_fw_config_filename to remove the duplicate code.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ifde714c19f7ab9fe08f870060037db190a80dbd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=untested on brya, but tested under Windows/Linux on all other
boards in the tree using Synaptics touchpads.
Change-Id: Ia9351185b918f2d6f2d2be110b88e8310d37a03f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Extend sd_hold to meet touchpad/touchscreen SPEC.
touchscreen:
tHD > 0.2 us
touchpad:
0.3 us < tHD < 0.9 us
After applied the change, the tHD meets reqirement.
touchscreen:
0.056 us -> 0.28 us
touchpad:
0.056 us -> 0.384 us
BUG=b:263340540
TEST=build and measure the timing meet SPEC
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I172d2ec8a4b16d8005106f55a37795cc72d69e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Configure eMMC DLL tuning values for Pujjo board Kioxia sku.
BUG=b:261676386
TEST=Use the value to boot on Pujjo successfully.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I46991f26571771620dcd94b90e1112484ade63bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as kano is using a converged firmware image.
BUG=b:253337338
BRANCH=firmware-brya-14505.B
TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
disable hardware write protect and software write protect,
flash and boot kano in end-of-manufacturing mode to kernel.
Cq-Depend: chrome-internal:5246998, chromium:4119763
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: I30ab7d829a6cb45b4e0cd38747501ba0eb6bd6cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71175
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust I2C speed for codec, TPM, touchpad, touchscreen.
BUG=b:260565911
TEST=Built and verified adjusted I2C speed
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Idcec6e401992d30dff01940c50473cba48cffc19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
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Enable wifi sar function for yaviks.
Use the fw_config to separate SAR setting for different wifi card.
BUG=259199095
TEST=build, enabled iwlwifi debug, and check dmesg
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I3ced65368ee66e084e58d66cff8f75147f665d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Update SX9324 RegProxCtrl0 register settings based on tunning value
from P-sensor vendor.
BUG=b:242662878
TEST=i2cdump -y -f 13 0x28 on Pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: If471a6fee5a3daeac1958709415b2d5e1329b81b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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To support an RPL SKU on lisbon, lisbon must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for lisbon so that it will use the RPL
FSP headers for lisbon.
BUG=b:246657849
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=lisbon emerge-brask intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
flash and boot lisbon to kernel.
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ie60c357ef0a2af2fec90df4a54e56f51ceb927d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70236
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Disable unused PCIE8 for fix system can not enter S0ix completely.
BUG=b:261915226
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Correct touchscreen setting to make touchscreen function workable.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=Built and verified touchscreen function
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ia98deae65ef0e2f501457331144b044e07431a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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pujjo support FM101 WWAN, add delay of FCPO# to meet warm reset toff
minimum 500ms requirement.
BUG=b:260380268
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I63e599e76bd8a15ca44717823411576fa4df1c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:252966799
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Change-Id: I175f7f39d6115d1f082575393c45734c7b02e346
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on nivviks and yaviks.
BUG=b:259716145
TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.
Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA-FQ
After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA
Change-Id: Iaddb24580bda77df0c70ff58eb098213f8b509ad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add wifi sar for lisbon.
BUG=b:260938760
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage
Change-Id: Ia347c4cf56bec971700bb53a5804e36e0bad82fb
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70483
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar for gladios.
BUG=b:260950906
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage
Change-Id: I4cd015f17c4ddd28414f51a873ae4afc37863708
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70605
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct touchpad setting to make touchpad function workable.
BUG=b:261393412
BRANCH=firmware-brya-14505.B
TEST=Built and verified touchpad function
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3c816ce4293ae362f0e5c18171f296d42b4307c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70440
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The EN_PP3300_SD gpio (GPP_H13) was configured as a no-connect, but
should be configured as an output.
This change configures GPP_H13 on brya0 and skolas to be an output.
BUG=b:261901759
BRANCH=firmware-brya-14505.B
TEST="emerge-brya coreboot chromeos-bootimage" and verify skolas boots.
Change-Id: Ia3f01e877a5fea3af9a6e746523ed395f3af3b8a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70512
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar table for pujjo intel wifi config.
Use fw_config to separate different project settings.
BUG=b:256042825,b:256042769
Test=emerge-nissa coreboot
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ibdbe1c0a477e47af9cbbc9bf73ac583d06ad7a0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70480
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Disable unused I2C2/I2C4 bus for marasov.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id1c41bfdca9b752e3f027e6b071629d67aa06761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70237
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Add new memory parts
- H58G56BK7BX068
- MT62F1G32D2DS-026 WT:B
- K3KL8L80CM-MGCT
BUG=b:261539879
TEST=run part_id_gen to generate SPD id
Change-Id: I74f35d1afad90c3b6a79679a8126904565695fbc
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70410
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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commit 52ccd293d7 ("mb/google/brya: Implement shutdown function for
dGPU") started unconditionally adding MPTS to the SSDT. On variants
with HAVE_WWAN_POWER_SEQUENCE selected, MPTS is already added to the
DSDT via wwan_power.asl. The duplicate definition results in a kernel
error:
ERR kernel: [ 0.109237] ACPI BIOS Error (bug): Failure creating named object [\_SB.MPTS], AE_ALREADY_EXISTS (20210730/dswload2-327)
ERR kernel: [ 0.109242] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20210730/psobject-220)
Don't add MPTS to the SSDT if HAVE_WWAN_POWER_SEQUENCE is selected.
There are no variants which use both, so this should only result in
empty MPTS methods being removed.
BUG=b:260380268
TEST=On pujjo, the SSDT no longer contains an empty MPTS method, there's
no kernel error, and the WWAN power-off sequence is met.
Change-Id: I9f411aae81ea87aa9c8fc7754c3709e398771a32
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70146
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PP1800_GPU_X should dynamically move from GPP_E18 to GPP_F12
depending on board revision.
PP0950_GPU_X (PEX) should remain on GPP_E10 for all board
revisions.
BUG=b:242752623
TEST=dGPU is functional on both revisions of the board
Change-Id: I20994fcac4d7b98ee893d5eb98b096c037d31d6c
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70320
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change FSP board type to Type3.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
check MRC log "Maximum requested frequency" is 4800
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I69365bc726b4faac4cedb94cc7b08baa06056c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70439
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable PCIe port 5 for WLAN device
BUG=b:261514079
BRANCH=firmware-brya-14505.B
TEST=Build and boot on marasov.
Ensure that the WLAN module is enumerated in the output of lspci.
localhost ~ # lspci
01:00.0 Network controller: MEDIATEK Corp. MT7921 802.11ax PCI Express Wireless Network Adapter
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I007501bb00e2b7b83de1292f3066874d07646cb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70442
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables V1p05 and Vnn external bypass VRs for Marasov.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id28305b02e86f5ac55382ac6d2bd5e0453aae9b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Adjust the bit fields in the FW_CONFIG for Proto Phase.
BUG=b:254404046
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=marasov emerge-brya coreboot
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ia71269918092655c11c2b37a26ec19123f759650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
Drop the __weak qualifier as this function is not overridden.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ica25b2bc4325ff9d27be672926b4e3b550c86e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
option STORAGE_EMMC 0
option STORAGE_NVME 1
BUG=b:239513596
TEST=FW_NAME=gladios emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I27baa2ca8c2b334fb81aa87b22c3b7c028c38cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
option STORAGE_EMMC 0
option STORAGE_NVME 1
BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Idd52112743ee0d64aca630e54511503607770d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
DmaProperty must only be present on endpoint devices.
BUG=b:259716145
TEST=TBD
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic5be85c3d13250646867f8c8f5950796ec339551
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add the RPL CPU power limits to kano and zydron's power limit table.
BUG=b:261127266
BRANCH=brya
TEST="emerge-brya coreboot chromeos-bootimage", flash zydron with
image-zydron.serial.bin and verify zydron boots successfully to kernel.
Change-Id: I369c5d7a9a3db0c3e7184a23b0f159ed715b5a50
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70238
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add WiFi SAR table for zydron.
BUG=b:260770999
TEST=build FW and checked SAR table can load by WiFi driver.
Change-Id: I8d5f966c7af3ac6d9923d4f6c851bfb340f31fab
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Adjust scl_lcnt, scl_hcnt, sda_hold value for I2C5 to meet
touchpad SPEC.
BUG=b:260540852
BRANCH=firmware-brya-14505.B
TEST=build, checked TP function work normally,
and measure the timing meet SPEC
tLOW ~1.72 us
tHIGH ~0.63 us
tHD ~0.69 us
fscl 383 kHz
Change-Id: I9036a604a90558911c4f8a492db9f1f0f28bf404
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Fine-tune eMMC DLL based on Xivu EVT system.
BUG=b:256538132
TEST=executed 3000 cycles of cold boot successfully
Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be
Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69892
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Refer to brask board to add audio settings for gaelin.
BUG=b:253177160
BRANCH=firmware-brya-14505.B
TEST=Able to verify audio playback on gaelin with kernel v5.10.
Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Modify USB2.0 port[4] settings to support camera.
BUG=b:238252678
BRANCH=firmware-brya-14505.B
TEST=with brask overlay changes, camera in camera app works
Change-Id: I42325b75e129429ee451ded6a2086fd3808e581a
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Add new audio sku configure for Pujjo board.
BUG=b:260538412
TEST=Boot to OS on pujjo and check that audio are configured
based on fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia9ddc683945002a0b19efd67006e1983b2eb9f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
FSP silicon discards the request if the Voltage Regulator or SoC does
not support the feature.
BUG:b:259057787
TEST:Verify that the feature is enabled by reading from pcode
No PnP regression observed
BRANCH=firmware-brya-14505.B
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7e318534f1429af8ec06048430966344ddd346a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69579
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch supports multiple camera modules based on FW_CONFIG.
BUG=b:251235140
TEST=Test the changes with ov2740/hi556 camera.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0a4f46d889e9f6c2898efee6825cf2d02252d87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
|
This patch enables crashlog for all brya projects.
BUG=b:190756531, b:259978562
BRANCH=None
TEST=emerge-brya coreboot chromeos-bootimage & ensure the crashlog
PCIe device 0xa.0 is enabled and intel-pmt kernel driver is
loaded.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ib632c8ac9ea7a4f0e0b08b96eb149f8ef1386be0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68526
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Add ACPI DmaProperty for ethernet devices.
BUG=b:259716145
TEST=Verified SSDT on google/osiris.
Before:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
}
}
After:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
}
}
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I647593fd02644d30cd21b60d8305c0ec55dc64cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70017
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:259716145
TEST=TBD
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ifaa0912b38129ed2db01fb78ed39c0db89e746fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70018
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Based on latest schematic to update the gpio table.
BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=marasov emerge-brya coreboot
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I03b443826d39182eaf23ad3e4e0ba8d6b8a93022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69180
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
Enable NVMe GPIOs based on fw_config and add NVMe to devicetree.
Note, eMMC and NVMe are not probed in devicetree. On first boot in
factory, the device needs to boot with unprovisioned fw_config, so all
storage devices should be enabled when unprovisioned. Currently,
devicetree disables all probed devices when unprovisioned. If we want
eMMC and NVMe to be probed, support needs to be added for enabling
probed devices when unprovisioned.
BUG=b:259211172
TEST=Verified by ODM. On craask, LTE and WCAM still work. On craaskneto,
eMMC and NVMe SKUs can both boot.
Change-Id: I76a056cddff2246cfb5bb26ddbdfc333b49d9aaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69958
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Follow thermal table from thermal team.
1. Modify TS1 passive policy to 68.
BUG=b:249446156
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69960
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it
makes sense to have a unified name across different device drivers.
BUG=b:259716145
TEST=Verified that the _DSD object is still present in the SSDT.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69937
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add conn0/conn1 for pch_espi.
BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5969d2941c02400788d66521680fcd13d3a6b13f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69785
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Declare touchscreen and touchpad under I2C3 and I2C5
BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=Built successfully
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifc865fc0c0c42af0d74272289c562e347fac3a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69467
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust SPD ID order
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
MT62F1G32D4DR-031 WT:B 2 (0010)
H9JCNNNCP3MLYR-N6E 3 (0011)
BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3a62cf355508debce387c48d9d089e73763b2bf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69784
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The brask doesn't include a real chassis so we don't need to configure
the fan setting in the overridetree.cb. Instead, we can leave the fan
running at full speed after the device boot up.
BUG=b:259643676
BRANCH=firmware-brya-14505.B
TEST=flashed the bios to the device and make sure the fan spinned
at full speed.
Change-Id: I6075b6171ca4d7b907679efd0ce7e355759385bc
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Based on the latest schematic to update the gpio table.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ifaf0629dcd77d21cf09fe84e760f1f22c075467f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Override devicetree configuration based on the latest gaelin schematic.
BUG=b:249000573, b:254375472
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=emerge-brask coreboot
Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Update devicetree setting per the schematic.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I8746d44daa43c06723bdfcac6803eb90a3c124b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This reverts commit 7203aa5c2dcb90e50356305cabbe062bd4f4dc76.
BUG=b:260138434
TEST=None
Cq-Depend: chrome-internal:5126951, chromium:4049177
Change-Id: Ieaa44a33a7c65d384581b5145821b449783ca3fa
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
For nissa, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.
BUG=b:234776154
TEST=Boot to OS on nirwen and yaviks UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.
Cq-Depend: chrome-internal:5102230
Change-Id: I68f963e17bc0dbf9db9adaaa3f96f06b8737523b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
BUG=b:253387689
Test:Boot to OS on craask and check SAR Proximity Sensor GPIO pin
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I2b2a2516890b68036e96d1a542e6a10a098cb6a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69790
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
field STORAGE 30 31
option STORAGE_UNKNOWN 0
option STORAGE_NVME 1
option STORAGE_UFS 2
end
BUG=b:254365935
TEST=emerge-brya coreboot.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I17f8a852808d279a1f2b08b364cd4e525a807560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69786
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all
references.
BUG=b:216485035,b:258126464
BRANCH=none
TEST=none
Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
BUG=b:235919755
Test=Check error message "Exposing GPIOs in Power Resource and _CRS"
not show in firmware log.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I21a47adde48555098d041b94d483cad308bdb717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Modify the chromeos FMD file for nissa variants to redistribute the
buffer in SI_ME region obtained due to CSE size optimizations to SI_BIOS
region.
1. Modify SI_ALL region size to 3712K. SI_DESC remains at 4K and SI_ME
is 3708K.
2. Modify SI_BIOS region to 12672K. This results in an addition of 32K
buffer each to FW_MAIN_A/B regions.
BUG=b:228936671
BRANCH=firmware-nissa-15217.B
TEST=Verify CSE FW update with new FMD and ME RW blobs on craask.
Cq-Depend: chrome-internal:5094491
Change-Id: I5ead2f81850a2aa79e677c7f271db672e235750a
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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|
+-----------+-------+-------+---------+-------------+----------+
| Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
| |(mOhms)|(mOhms)| (A) | (A) | (msec) |
+-----------+-------+-------+---------+-------------+----------+
| IA | 2.8 | 2.8 | 80 | 43 | 28000 |
+-----------+-------+-------+---------+-------------+----------+
| GT | 3.2 | 3.2 | 40 | 23 | 28000 |
+-----------+-------+-------+---------+-------------+----------+
- IA TDC current from 20A to 43A.
- GT TDC current from 20A to 23A.
BUG=b:256754175
TEST=Build test image and use PTAT to check IA and GT value
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: Ife36655f077bae567bff3c3e33f779c990cf5ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69135
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Tune timing between power on and reset on SD device RTD3.
BUG=b:250746988
TEST=Use the value to boot on Pujjo successfully.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I1ea77ec8381000249229653f1c0b9044bdf7866d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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ALC5682-VS/ALC5682-VD use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.
ALC5682I-VS: _HID = "RTL5682"
ALC5682-VD: _HID = "10EC5682"
BUG=b:246491349
TEST=ALC5682-VD/ALC5682-VS audio codec can work.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I60d5e0af7e2dabd134c8059eaeac388d40ac2073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable ISH driver and set firmware name as "adl_ish_lite.bin"
BUG=b:242291814
TEST=boot into kernel, and check dmesg
"ISH firmware intel/adl_ish_lite.bin loaded"
Change-Id: I4badabba1a0cfceb77fc91f21953496152f19615
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69606
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add power limits for the RPL SKUs of Agah.
BUG=b:258432915
TEST=build and boot ADL based Agah. RPL based testing
when hardware becomes available.
Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69419
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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ELAN updated the datasheet, the HID/I2C protocol's T3 delay
time is 150ms now. Modify the volmar's delay time to follow
the requiremnet.
BUG=b:257073343
TEST=Build firmware and measure the T3 timing of resume
and boot up on volmar DUT.
Run Suspend/Resume with UI test and got pass.
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I40a30ed567cd676d0a9373527d93fe51f89d39e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69559
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Correct G2 touchscreen HID to GT75CH02.
BUG=b:235919755
Test=Dump the SSDT on craask and check the HID had been modified.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Iad32e8cbd534dc43fca24d881092f3477ca1a4e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69600
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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GPP_H13 should be reset when going to S5. Update it to do so on
PLTRST
BUG=b:240617195
TEST=Measured on Agah that PP3300_SD_X goes off in S5.
Change-Id: I959f92f2c486e0ca5cb4269b271c163b4c4925d4
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69340
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add TPM I2C bus for gaelin in Kconfig.
BUG=b:249000573
BRANCH=firmware-brya-14505.B
TEST=Build "emerge-brask coreboot" and can boot to OS.
Change-Id: Idaac11111a9ba7df0929267567e4730b2811f5f0
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68886
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Some nissa devices want to disable boot from SD card. Since nissa has a
single shared depthcharge target, add a program-wide fw_config to allow
disabling it.
BUG=b:253003881
TEST=With depthcharge change, set SD_BOOT_DISABLE on nivviks and check
SD card is not initialised in depthcharge.
Change-Id: I1a3a533e4e74e48d9ce4a9678b812cb62ce2066b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69541
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The SI_ME subregions were added to support using the CSE stitching tools
(cse_serger). Use of the stitching tools has been reverted and probably
won't be re-enabled soon, so the subregions are not currently used by
anything. They also don't match the actual region sizes chosen by the
FIT tool, so remove them to avoid confusion. The other option would be
to manually keep them in sync with the sizes chosen by the FIT tool, but
this would be extra manual effort without much benefit.
BUG=None
TEST=Build and boot on nivviks
Change-Id: I993e07a060445ab8de1b0e40a023e8248867c53c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69540
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
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Configure the rcomp, dqs and dq tables based on the schematic.
BUG=b:254365935
BRANCH=None
TEST=Built successfully
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69149
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
marasov variant.
BUG=b:254365935
TEST=FW_NAME=marasov emerge-brya coreboot
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I4d155fb35424d1ec12e825ca0aab233bd3cd607e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69376
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Request by RF team, remove RFIM related settings to disable it.
BUG=b:239657092
Test=RF team test on DUT and check it's disable
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I1eb4d93c2821cb067628dc1228c6c522d292c739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Modify touch screen hid for Pujjo board.
BUG=b:258586760
TEST=Use the value to boot on Pujjo successfully.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia3b374de8cba2125c478814a1890a4b6831715b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Enable RPL support for Agah.
BUG=b:258432915
TEST=build and boot ADL based Agah. RPL based testing
when hardware becomes available.
Change-Id: I5437dbf9e7812367a280d1ed659f286fb9b62a68
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69398
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Disable the unused fingerprinter(FP) gpio for zavala by fw_config
FPMCU_MASK field.
BUG=b:250807253
TEST=build firmware and veriify the FP function on volmar DUT
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I0af1b7c3e4829ecab98525ead4f078c3eb6485d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69465
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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BUG=b:234776154
TEST=Build and boot Marasov UFS, copy ISH firmware to host
file system /lib/firmware/intel/adl_ish_lite.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adl_ish_lite.bin loaded
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic53a3cbdf83825adc27f37877a14f4f405d4a5ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69377
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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This patch ensures that Marasov selects the ISH driver for
devices with UFS enabled.
BUG=b:256566011
TEST=Able to build Marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I97a0aa3bc6976be32ddbf1fc6b37c16bb62a62e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69379
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Support GL9763E as a eMMC boot disk.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I2b29309615df381f1e24f29fc048c6f9bf216b7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69425
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
gladios variant.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69424
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
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To support an RPL SKU on marasov, marasov must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for marasov so that it will use the RPL
FSP headers for marasov.
BUG=b:254365935
BRANCH=None
TEST=FW_NAME=marasov emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I7874420c0fb51b9cc616cd979ffc9349c381602e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69367
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
MT62F1G32D4DR-031 WT:B 4 (0100)
H9JCNNNCP3MLYR-N6E 5 (0101)
BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69311
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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update devicetree setting per the schematic
BUG=b:254365935
BRANCH=None
TEST=Built successfully
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:257879909
Test:Boot to OS on craask and check stylus GPIO pins
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I7e3a2583187c8a8e2616a5272b5a7a61debe982b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69138
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Request by thermal team, make below changes:
1) tdp_pl2_override: 12 --> 25
2) pl1.min_power: 3000 --> 5500
3) pl1.time_window_max: 32 * MSECS_PER_SEC --> 28 * MSECS_PER_SEC
4) pl2.min_power: 12000 --> 25000
5) pl2.max_power: 12000 --> 25000
6) pl2.time_window_min: 28 * MSECS_PER_SEC --> 1
7) pl2.time_window_max: 32 * MSECS_PER_SEC --> 1
BUG=b:239495499
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68523
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
|
|
Update SX9324 related settings based on tunned values from the ODM.
This patch supports both legacy and upstream Linux's SX9324 driver.
BUG=b:242662878
TEST=i2cdump -y -f 13 0x28
(Verified register values on Pujjo)
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I34d8073ffe93e6939f8da0cd7efb8667c0e9ac37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69366
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar table for craask/craaskbowl.
Use fw_config to separate different project settings.
BUG=b:247652032,b:251287099,b:251287101
Test=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Add new ram_id:0 (0000) for memory part H9JCNNNCP3MLYR-N6E.
DRAM Part Name ID to assign
H9JCNNNCP3MLYR-N6E 0 (0000)
BUG=b:257867226
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: If663afbcd2e0457636f4a1c7475f1e3e40f0dd96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
