| Age | Commit message (Collapse) | Author |
|---|
|
Tuning i2c frequency ,timing ,Waveform meet to SPEC
i2c frequency :
I2C0=>399.8khz / Setup Time:1765ns / Hold Time:82.35ns.
I2C1=>390.4khz / Setup Time:1.788us / Hold Time:70.58ns.
I2C3=>308.7khz / Setup Time:1.482us / Hold Time:0.4us.
I2C5=>390.8khz / Setup Time:1.218us / Hold Time:0.405us.
BUG=b:275061994
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot,
EE check OK with test FW and TP function is normal.
Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74880
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
Camera LED will blink several times as sensor is being probed during kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:274634319
TEST=Build and boot on Craask. Verify & observe Camera LED blinking behavior.
Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7
Signed-off-by: Jimmy Su <jimmy.su@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74728
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update devicetree to support ELAN I2C generic touchscreen.
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I2779c2930d89ff42233f9b20bd8abdf6dc00c0e0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74776
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
The signals for the NV33 regulator were swapped (enable and power
good). Switch these back to the way they should be:
GPIO_NV33_PWR_EN GPP_E1
GPIO_NV33_PG GPP_E2
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ic2a53103e1feadd7ecebd4bed02dcc34410b8e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
Remove rtd3 for emmc device on taeko
BUG=b:271003060
TEST= emerge-brya coreboot, flash to DUT and can boot to OS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Remove rtd3 for emmc device on taniks
BUG=b:271003060
TEST=emerge-brya coreboot, flash to DUT and can boot to OS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
The patch disables Tccold Handshake to prevent possible display
flicker issue for Omnigul board. Please refer to Intel doc#723158
for more information.
BUG=b:279539826
BRANCH=firmware-brya-14505.B
TEST=Verify the build for Omnigul board
Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74737
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
USB port 6 connects to a USB front camera, it should always probe.
Remove probe by rear camera fw_config.
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I554046718f6e0eb7197970f9a3808b3e1ea7f99c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Update devicetree
-Enable USB2 port5 for WWAN
-Update OVTI8856 setting
-Update USB2/3 Type-A 0/1 port location
Probe devicetree based on FW_CONFIG
-pen garage
-rear mipi cam
-USB WWAN
BUG=b:273791621, b:276369170
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Yavilla board memory id setting references to yaviks.
This CL aligen it with yaviks.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
H58G56BK7BX068 3 (0011)
MT62F1G32D2DS-026 WT:B 3 (0011)
K3KL8L80CM-MGCT 3 (0011)
H58G66BK7BX067 4 (0100)
MT62F2G32D4DS-026 WT:B 4 (0100)
K3KL9L90CM-MGCT 4 (0100)
H58G66AK6BX070 5 (0101)
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id
Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
To aid in layout, the PCI ports for LAN and SD card were swapped.
SD Card is now on RP3 (clksrc 4)
LAN is now on RP8 (clksrc 3)
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The patch disables PCH USB2 PHY power gating to prevent possible
display flicker issue. Please refer Intel doc#723158 for more information.
BUG=b:279117758
BRANCH=firmware-brya-14505.B
TEST=Verify the build for marasov board
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74627
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Google Brya variants like Nissa family selects
`SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` to store CSE FPT
information.
BUG=b:273661726
TEST=Able to build and boot google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74387
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN.
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia87b5f9d8300d6263c84a586256424799d3a45b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73382
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers,
hence it makes sense to have a unified name across different device drivers.
BUG=b:278310435
BRANCH=firmware-brya-14505.B
TEST=Verified that the _DSD object is still present in the SSDT.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5a69a47e67f6acaad5a5d1b67e437c5a41bebf3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74499
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as crota is using a converged firmware image.
BUG=b:267249674
BRANCH=firmware-brya-14505.B
TEST="FW_NAME=crota emerge-brya
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage"
Cq-Depend: chromium:4430832
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I448c58f93fddc44904c1f5ef3f8939618eff536f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Add supported memory part in mem_parts_used.txt, then generate.
K4UBE3D4AB-MGCL
BUG=b:267539938
TEST=run part_id_gen to generate SPD id
Change-Id: Iee41bb4511f2d77e5ddc2798f9d4db6137ed818d
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74497
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for
audio, TPM, touchscreen, and touchpad.
Tuning i2c frequency for omnigul
I2C0 - Audio CLK : 293.7khz
I2C1 - TPM CLK : 388.8khz
I2C3 - Touch Screen CLK : 294.8khz
I2C5 - Touch Pad CLK : 389.2khz
BUG=b:275061994
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot, and measure i2c clock.
Change-Id: I7c4fdf0e003318a69b870b487a60accefbc0ffed
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Update GPIO configs based on latest schematics (revision aabe36)
Move GPP_D4->GPP_A13 (BT_DISABLE_L)
Swap GPP_E3<>GPP_E8 (WIFI_DISABLE_L and PG_PPVAR_GPU_NVVDD_X_OD)
Move GPP_A13->GPP_A20 (GSC_PCH_INT_ODL)
BUG=b:269371363
TEST=builds
Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Add G2 touchscreen GTCH7503 for craaskino.
Use SSFC to separate touchscreen settings.
Bit 38-41 for TS_SOURCE:
(1) TS_UNPROVISIONED --> 0
(2) TS_GTCH7503 --> 1
BUG=b:277979947
TEST=(1) emerge-nissa coreboot
(2) Test on craaskino with G2 touchscreen
(3) Test on craaskino with elan touchscreen
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I636f21be39f26a617653e134129a11479e801ea2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
All the variant will use the same dGPU, so make PCIEXP_SUPPORT_RESIZABLE_BARS common.
BUG=b:277974986
TEST=abuild -a -x -c max -p none -t google/brya -b hades
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: If8618f2da3133c6b52427375c55a69d7014c4881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74371
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
Implement the GPS_REQUESTDXSTATE function which forces the
current D notifier state to re-report.
TEST=verified that notifications are forced out when invoked using
acpiexec
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I6dab9b793fe1d0b1c875eddbe6ae324d2894efe6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Currently the DNOT function first checks to see if the current DNOT
value has already been reported. Add support to allow forcing regardless
if it had been sent already.
TEST=confirmed that when enabled, all events notify. When disabled, only
events on value change are notified.
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I7a93cca6a8f922574dd46b46572b230755db9aa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Currently the value was being truncated to 4 bytes. Change so that
the full 8 byte value is passed.
TEST=verified function returns expected value using acpiexec
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Icfc775de680e328a2b240595223d7098fee3dc3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This function adds support to convert a integer into a 8 byte buffer
TEST=verified returned buffer is as expected using acpiexec
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I89eb50f1452657c26b97eb5609ed956fa8ee8117
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The logic was not equals, rather than the intended greater than or
equal to for checking the minimum GPS revision.
TEST=version check passes as expected now
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I66bf1fc32295e1b9e9c41c661ea8e395a1592a86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Yavilla is a variant of yaviks which is almost identical
to yaviks, so is reusing the yaviks coreboot variant.
so update the GPIO tables to handle these based on fw_config.
BUG=b:277148122
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I831b199055c931e7a4a393eeb9e75e83c8ae3c3a
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74264
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select hdmi vbt bin files based on MB_HDMI field of FW_CONFIG.
BUG=b:277148122, b:276369170
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I210003c27c83155dd5a768c1a6cdcfd8c849d256
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74262
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Yavilla will leverage yaviks FW build.
It has one additional USB Type-A0 port, support stylus and support WWAN.
Here update devicetree based on FW_CONFIG for yavilla's design.
-Enable USB2 port3 and USB3 port1 for USB2/3 Type-A0
-Enable USB2 port5 and USB3 port3 for WWAN
-Enable pen garage
-Enable rear mipi cam
-Enable Synaptics touchpad
BUG=b:277148122, b:276369170
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I38dbcf5920d12adb1f84885bdfa4c2f2faf2eb9e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
These new memory are added for yavilla.
DRAM Part Name ID to assigna
H58G66BK7BX067 4 (0100)
MT62F2G32D4DS-026 WT:B 4 (0100)
K3KL9L90CM-MGCT 4 (0100)
H58G66AK6BX070 5 (0101)
BUG=b:277148122
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id
Change-Id: I3c48b9763f54e2e69f7c2d494fefbabedab2a389
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch configures external V1p05/Vnn/VnnSx rails for Uldren
to follow best practices for power savings – untested though.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:272829190
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74335
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add GPU power sequencing changes for the Hades baseboard and variant.
Some signals were added, moved or inverted.
Based on implementation from Agah.
Moved signals:
GPIO_1V8_PWR_EN GPP_E11
GPIO_NV33_PWR_EN GPP_E2
GPIO_NV33_PG GPP_E1
New signals:
GPIO_NV12_PWR_EN GPP_D0
GPIO_NV12_PG GPP_D1
Inverted signals:
GPIO_FBVDD_PWR_EN GPP_A19
ifdef's will be dropped once the Agah variant is retired.
BUG=b:269371363
TEST=builds and verified on Agah that DGPU is still detectable (lspci)
Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
Without gpio.c compiled in, SMMSTORE will fail to initialize and hang.
Add a conditional inclusion so gpio.c is compiled in SMM when SMMSTORE
is selected.
TEST=build/boot google/banshee with SMMSTORE support enabled
Change-Id: If049cba98f13f060807058029306dcad2ada2d49
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815
retimer on USB U1/U2 transition. The usb_lpm_incapable config is
used to disable USB U1/U2 transition for these Type-C ports.
BUG=b:277149723
BRANCH=firmware-brya-14505.B
TEST=Plug in device and check LPM sysfs nodes are disabled
localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u1
disabled
localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u2
disabled
Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ron Lee <ron.lee@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=b:271788117
TEST=build FW and system power on.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
|
|
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32.
Revert initial change as it was causing a boot failure when
transitioning into recovery mode.
BUG=b:276927816
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas
SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into
recovery mode.
Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add Alder Lake (ADL) and Raptor Lake (RPL) dptf settings for omnigul
BUG=b:273415170
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I8280f82ff1534ea63bcb448da231712bb4abd6d3
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
CSE performance data timestamps are different for version 1
Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch
moves the current ADL/RPL timestamp definitions to a separate
header file. It marks current structure as version 1.
BUG=b:259366109
TEST=Boot to OS, check ADL/RPL pre-cpu timestamps.
Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
|
Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2
RX signal integrity issue.
BUG=None
TEST=build FW and check Type-A USB3 port0/port1 RX pass
Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Add CPU power limits support and values for RPL on Hades
BUG=b:269371363
TEST=builds
Change-Id: I22ef56152abe5a23067c5e923b07d60dc9fac8e7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73895
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add override devicetree based on schematics(ver. 20230308).
BUG=b:272829190
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I9cd918c6a48cc6007a18c5aa94afe31fd9608718
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73974
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
|
Add the 28W TDP version of the ADL-P with MCHID 0x4629.
Verified that all 28W SoCs have the same PL1/PL2 defined
in Intel document #655258 "12th Generation Intel Core
Processors Datasheet, Volume 1 of 2".
Fixes the error seen in coreboot log:
[ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration
Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
|
|
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure GPIOs according to schematics(ver. 20230308).
BUG=b:272829190
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Id414c9b0d94faffd2d71c348fc7146a6101196e9
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
|
Initial hades GPIO config. Combination of original brya basebaord,
Agah and new arbitrage output for hades design.
Also moved GPIO config to the non baseboard variant model as we did on
rex0.
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I2a850240dd7f3ddf137d6a2ebe8a147f8976c16b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:273791621
TEST=emerge-nissa coreboot
Change-Id: I1a6013e0ad0c430d83bbbad4b92392c8c4815b0d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Update devicetree according to yavilla's design.
Add Kconfig for TPM I2C bus.
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I1b44436a7f93d62764d0451c738ae33976a24a15
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Update the mem_parts_used.txt, generate Makefile.inc and
dram_id.generated.txt for this part.
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 5 (0101)
BUG=b:267249674
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I20a12a58d8a3d66a901a14569ca710acba3c05f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73920
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Configure GPIOs according to schematics.
BUG=b:273791621
TEST=emerge-nissa coreboot
Change-Id: I5a522b59468667d20674d55597cc06975bc12ab5
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
|
|
Add WIFI SAR table for omnigul.
BUG=b:273170023,b:273652516
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I2db057371754961503cfdc59f21c365fc82672c4
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73940
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Enable SBU orientation handling by SoC for both USBC port2 and USBC
port3.
Constitution USBC port1 has retimer but USBC port2 and USBC port3 don't,
they do not flip the data lines, hence we need to set bits for USBC ports.
Change-Id: I4c5dfdba6c38c6e2f308b281ed316bb687ad8d8b
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The PCIE RP 9 on taeko is for eMMC.
Correct the comments to prevent confusion.
BUG=b:271003060
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib49942b682d1817af9e8b4b61044aa170e18fea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Follow 03_16 schematic to add the device tree.
BUG=b:272816611
TEST=abuild -a -x -c max -p none -t google/brya -b hades
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I85a05fec816954fd3408feccae84e0b9860ecdc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73838
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
GSPI is not used, remove it.
BUG=b:271199379
TEST=abuild -a -x -c max -p none -t google/brya -b hades
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I55d3f5119bc502621bdeae63b3d1e4cf43582038
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
K3KL6L60GM-MGCT 1 (0001)
MT62F1G32D2DS-026 WT:B 2 (0010)
K3KL8L80CM-MGCT 2 (0010)
H58G56BK7BX068 2 (0010)
BUG=b:270103716
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ia53c2be2ec606f42ac8bca06103b028e62ae6dbc
Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
|
|
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56BK7BX068 1 (0001)
MT62F1G32D2DS-026 WT:B 1 (0001)
K3KL8L80CM-MGCT 1 (0001)
H58G66BK7BX067 2 (0010)
MT62F2G32D4DS-026 WT:B 2 (0010)
K3KL9L90CM-MGCT 2 (0010)
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id
Change-Id: I82919919ec33d6bf9d86132490df754873b5df88
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Create the yavilla variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_YAVILLA
Change-Id: I4539090da5e1db474a8f58a42aecc38659959f75
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Add new ram_id:0010 for Micron MT62F1G32D2DS-023 WT:B.
The RAM ID table has been assigned as:
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
H58G56BK7BX068 0 (0000)
MT62F1G32D2DS-026 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H58G56BK8BX068 2 (0010)
MT62F1G32D2DS-023 WT:B 2 (0010)
BUG=b:273138520
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: Idc08624469590096047e5f77fb2e4ffb733f09ec
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73726
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
|
|
Rwmove temp sensor 3 for taniks since we do not use it.
BUG=b:265075696
TEST=emerge-brya coreboot, flash to DUT and will not see error messages
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib2c0cc8f1b2e65616c71d66632144ac89ca09fa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
BUG=b:271373437
BRANCH=none
TEST=Verify USB-A device could wake up Aurash.
Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: I67fc02d6c5660e0e3d1ab95bbda8ace1dc14b524
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73414
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify USB C1 mux_conn to 1. It should match ec settings.
BUG=b:272394875, b:272667290
BRANCH=firmware-brya-14505.B
TEST=Plug USB-C hub in USB C1 and could recognize USB drive and hdmi.
Change-Id: I61b77405d1790b044174cef954e5bf910141f424
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
1. Modify irq_gpio GPP_H0 -> GPP_A23
BUG=b:272218750
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I8e178b149015ed8027b547e4c2109b3aef8a7484
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
1. Add generic.stop_gpio = GPP_C6
2. Add c.stop_off_delay_ms = 2
BUG=b:271966059
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I33857443d8a68e7b50ac5f8f08afc017fe4f5a59
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Create the uldren variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:271513530
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ULDREN
Change-Id: Ibbcd34fb4ef1f7464f0c94d2fcf75280c3eed6be
Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73680
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Allow USB2/3 hotplug event to wake up S0ix.
BUG=b:236189998
BRANCH=firmware-brya-14505.B
TEST=Verify USB-A device could wake up Kinox
Change-Id: I8aeeeac6c21289b70bdc7ffddc57687ac39e8456
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
1. device ref pcie_rp11 -> pcie_rp9 on.
BUG=b:270657362
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: If23785f42466ba94f33d4d15dde96de29dbb3a1e
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73530
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable ELAN eKTH5015M touchscreen.
BUG=b:271966059
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I41eac949f21a48098b445f8d1b05f308672f7ab8
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Decrease Touch i2c delay during power-on sequence from 300 ms to
150 ms to make S0ix resume time meet requirement.
BUG=b:264199989
TEST=Run the following test from chroot.
test_that -b {BOARD_NAME} {device IP} f:.*power_UiResume/control
Check seconds_system_resume value less than 500 msec
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ib81a9c1a90589b8b08e6ce6471db2abef96047ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73532
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove GPP_D11,GPP_D12 in ramstage, follow baseboard brask setting.
TEST=emerge-brask coreboot
make sure HDMIA can display
Change-Id: I953170f006699e3dc9d6111ded8234f66b9162c7
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
EC_HOST_EVENT_GPU was renamed from
EC_HOST_EVENT_USB_CHARGER and thought to no longer
be used. It was subsequently removed in
I9e3e0e9b45385766343489ae2d8fc43fb0954923
Add back the mask for this event as it is infact
required on certain Brya (Agah) and Hades variants.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
BUG=b:216485035,b:258126464,b:266631157
BRANCH=none
TEST=D-notifier events are received again from EC
Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73217
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Extend sd_hold to meet touchpad/touchscreen SPEC.
touchscreen:
tHD > 100 ns
touchpad:
900 ns > tHD > 300 ns
After applied the change, the tHD meets reqirement.
touchscreen:
35 ns --> 260 ns
touchpad:
43 ns --> 368 ns
BUG=b:271524470
TEST=build and measure the timing meet SPEC
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Iec2f72da80ffe8d4dd494caabbe1a97e52a81e78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Add SODIMM support, drop the solderdown based on schematics.
BUG=b:271199379
TEST=abuild -a -x -c max -p none -t google/brya -b hades
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I85ec79c3d8f1147a875c4d04017bb50347121ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Fast VMode makes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:270242461
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I82c2016d9dfb39ff7b372815737d4ae62875340c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73373
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
To support an RPL SKU on taeko, taeko must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for taeko so that it will use the RPL
FSP headers for taeko.
BUG=b:270242461
BRANCH=firmware-brya-14505.B
TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
flash and boot taeko to kernel.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Cq-Depend: chrome-internal:5544049, chromium:4302529
Change-Id: Ic97400555dabb237325e7c4a8d5edcbb4779cdb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Add minimum device tree. Leave IOs default disable to optimize variant
override complexity.
BUG=b:271199379
TEST=abuild -a -x -c max -p none -t google/brya -b hades
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ibb056c07193b4265352a9ec74829dcf02a9340bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
BUG=b:230398487
BRANCH=none
TEST=Verify USB-A device could wake up Moli.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I1c8daf62dabe674a39b1416d886f9e470ae23a5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73174
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The skolas baseboard is no longer needed, so this change removes the
baseboard files for skolas and adjusts the config settings to that
variants that used to select BOARD_GOOGLE_BASEBOARD_SKOLAS now
select BOARD_GOOGLE_BASEBOARD_BRYA and SOC_INTEL_RAPTORLAKE.
BUG=b:271470530
TEST="emerge-brya coreboot chromeos-bootimage", flash image-skolas.bin
onto a skolas and verify it boots to kernel.
Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Fast VMode makes the SoC throttle when the current exceeds the I_TRIP
threshold.
TEST=FW_NAME=constitution emerge-brask coreboot
Change-Id: I1e68f708b7740567e24f8a3ddb9832aeec7ee6b5
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73247
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Pablo Ceballos <pceballos@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The DC boost bit was intended to be in the Controller Params word rather
than its own byte. Correct this error.
BUG=b:214581372
TEST=build
Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73216
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:270640775
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Change-Id: I35f577e1bab0f8dda10061903df13730e2c8ee04
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
To support an RPL SKU on osiris, osiris must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for osiris so that it will use the RPL
FSP headers for osiris.
BUG=b:270640775
BRANCH=firmware-brya-14505.B
TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
flash and boot osiris to kernel.
Cq-Depend: chromium:4290627, chrome-internal:5516851
Change-Id: If8de42a82fd85ffa8b9836e6024f119bc798f4fc
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Remove world-facing microphone for xivu360.
Switching to world-facing camera will use the
user-facing microphone to record sound.
BUG=b:263927799
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ibb720974b6488ce4453081e0bc5b4e7f34a6b0f6
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
To support an RPL SKU on constitution, it must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for constitution so that it will use the RPL
FSP headers.
BUG=b:267539938
TEST=emerge-brask intel-rplfsp coreboot
coreboot-private-files-baseboard-brya
Change-Id: Ie4f5eb6ebb372ad07308ff25c9eb69a83793c656
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73246
Reviewed-by: Pablo Ceballos <pceballos@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update override devicetree based on schematics.
BUG=None
TEST=FW_NAME=constitution emerge-brask coreboot
Change-Id: I883a806950821e6306242975764930035a94888e
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73110
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pablo Ceballos <pceballos@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
|
|
This reverts commit 3eb17b91daac0b3acaffb01568d724d23c6f0eea.
Reason for revert:
PLTRST only keeps 18xms and it's too short for eMMC disk fully reset.
Change-Id: If4277cb600bfe4e071959dacaf204fe7d3518f68
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73202
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This reverts commit 0e0f9e51c4c4f190cbe7ef5bffa138601c644d3c.
Reason for revert:
PLTRST only keeps 18xms and it's too short for eMMC disk fully reset.
Change-Id: I13b93747bdb4d39de1ffcfdc020648871fa6e048
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73203
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Update GPP_E12,GPP_E13,GPP_H19 in ramstage.
Update GPP_F11 in bootblock.
TEST=emerge-brask coreboot
Change-Id: Icdca7f574282da140ec64cea9cdda3ebccbe3eb8
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73194
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Pablo Ceballos <pceballos@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control
the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
This new option is hooked with `SkipMbpHob` UPD and is always disabled
for RPL & ADL-N based ChromeOS platforms.
It is not disabled for ADL-P based platforms because ADL-P FSP relies
on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit
sync doesn't occur if no MBP HOB, so it results S0ix issue. This
limitation is addressed in the later platforms so creation of MBP HOB
can be skipped for ADL-N and RPL based platforms.
This made skip_mbp_hob SOC chip config variable redundant which is also
removed as part of this change.
BUG=none
TEST=Build and boot to Google/Taniks.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate
when the state of charge drops to low_battery_shutdown_percent.
BUG=b:255465618
TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898)
Verify system resumes from s0ix and then enter S5 on nivviks with steps:
1. disconnect AC
2. powerd_dbus_suspend --disable_dark_resume=false
3. fakebatt 5
4. fakebatt 4
Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9
Signed-off-by: Ivan Chen <yulunchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Package C state demotion is now disabled for all RPL SoCs from within
soc/intel/alderlake/fsp_params, so no need to duplicate that in the
skolas devicetree.cb.
BUG=268296760
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Change-Id: I1c630e2efbdddd18a5423c79b73269e9b1be79c7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
BUG=b:265611305
TEST=Reboot test 2500 times pass
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: I2b114cac58a7fadeaee6d48996cb8b51f192e78f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Add a new baseboard for hades, an Intel RPL based reference design.
Also, add variants for the reference boards hades. This commit is
a stub which only adds the minimum code needed for a successful build.
Need update gpio and memory DQ pins after final shchematic comes out.
BUG=b:269371363
TEST=abuild -a -x -c max -p none -t google/brya -b hades
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
Initial Aurash configuration base on moli design.
1. Set up gpio.
2. Add memory config.
3. There is no SD card setting on aurash, remove it from overridetree.
4. Follow moli psys schematic design.
5. Enable BT offload.
BUG=b:269063331
TEST=emerge-brask coreboot.
Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: Ia9088cc2937bab72c8c22af592392384a10616a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
|
|
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B
5) Hynix H58G56BK8BX068
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I1f650c7e90804e871572f42ac925da85afd7f9d3
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72886
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
|
|
Configure GPIOs according to schematics
TEST=emerge-brask coreboot
Change-Id: Ib27f1c334cad47b3be57f57b7cc8ca5530118328
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72945
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust timing parameters on i2c1 and i2c2 to meet timing requirements.
For SCL, the t-high time is now over the min 600ns requirement
for 400KHz operation (measure at over 700ns). Also, this change
does not violate other parameters - rise time, setup time and hold time.
BUG=b:264704732
TEST=Verified all timings meet spec now
Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The NVPCF DSM subfunction specified a incorrect checksum.
Update this function to the proper checksum of 0xaf.
BUG=b:214581372
TEST=build
Change-Id: Ib58bd6cc10703ca67a7a4f520273865a95a4702b
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This reverts commit e30695dbe196ea42864ad03af799706eaae11f02.
for meet thermal criteria, modify PS1/PS2 cutoff to default value
BUG=b:229803757
BRANCH=brya
TEST='FW_NAME=vell emerge-brya coreboot'
Change-Id: Ie009788116f1e25db8aed2df58102a316a8aeef2
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72833
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
