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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:237421399
TEST=Verify the build for gimble board
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie66c9679c985215ad7f1a5ae76560b839ea95702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65474
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CB:63368 added a workaround of driving EN_PP3300_WLAN_X low in bootblock
to prevent a kernel crash on warm reboot. The crash has been fixed in
the kernel, so remove the workaround.
Kernel fix:
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3463465/
BUG=b:225261075
TEST=Wifi works on nereid, warm reboot doesn't crash the kernel
Change-Id: Idb5547e65ea934954326fcc740b14a83c939432e
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Fixes a bug in Makefile.inc.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2664df961a1fc0cd904a5e742face20c3fc8c3c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65450
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Debug FSP is ~850KiB larger than release FSP and we don't have
sufficient space for nissa flash layout.
Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a
room for it.
Note: This fmd will only used for internal testing/debugging and not for
the firmware in released devices.
BUG=b:231395098
TEST=build with CONFIG_BUILDING_WITH_DEBUG_FSP
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Idb17f003285575e80feb86bb292b95daf0f5b3b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Disabling the ASPM for I225V will cause I225V suspend fail, so remove ASPM_DISABLE for I225v.
BUG=b:235565637
TEST=emerge-brask coreboot and check LAN_I225V sku can boot into OS.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Id4505a713a3d92cb66c189cc2963111b6e90f092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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DDR interfaces emit electromagnetic radiation which can couple to the
antennas of various radios that are integrated in the system, and cause
radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for Nivviks variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=b:237238786
BRANCH=None
TEST=Build and boot Nivviks.
- Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: Iea5c6e0c404efb8231321701ea9282347e01f75d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Kernel driver will en/disable the IRQ when suspend/resume. If lock
the pin, driver can't change the status which causes the unexpected
behavior. Device will wake when insert the pen. This is workaround
until we figure out the correct setting for driver.
BUG=b:233159811
TEST=Pen garage wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ifc7b1e52a24c0e7bd54664d59870cb09536ef868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65380
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:231690996
TEST=gpios are the same in kernel pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I67a466fac478b2a3a682451174fbdcdd67816769
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Based on schematic and gpio table of pujjo, generate overridetree.cb
settings for pujjo.
BUG=b:235182560
TEST=FW_NAME=pujjo emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I47b10d03798004d1f3e398070acb2cbad46900b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
skolas4es variant.
BUG=b:230773725
TEST=None
Change-Id: I12b05cdacdd26bfffff47b7a3fb127aa7778f15d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65493
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed. After confirmed with the owner, the expect behavior is
only wake when eject the pen.
BUG=b:233159811
TEST=EC wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7a82e5e8935c9ea27e923661f66809e9169bc86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65379
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Add MIPI WFC based on schematics
BUG=b:236576117, b:235446911
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I85bd2ba187729a55c00369b218ca0414e0162b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Follow latest schematic to modify SPI flash to 16M.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I56be68b962c38d3f885dcf25a0251b8d9ab6ff3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65446
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Modify ddi_ports_config based on schematic Kinox_SCH_20220602.pdf.
DDI_PORT_A = DP
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP
DDI_PORT_2 = DP or HDMI
BUG=b:233338341
TEST=Boot to Chrome OS and check all display port working
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib2dbb34af1f85585b77638710d3799520c3f016f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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In order to improve gpio merge mechanism. Change iteration override
to padbased table override. And the following patch will change fw
config override with ramstage gpio table override.
BUG=b:231690996
TEST=check gpios in pinctrl are the same.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3d0beabc2c185405cb0af31e5506b6df94e9522c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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We have clarified the powerdown sequence with Nvidia, and the EEs have
come up with this modified sequence which still meets the requirements
from the hardware design guide.
BUG=b:233959099
TEST=Verified by ODM and EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I37715165ab488f994c825fb9ff532ebf8d7f4cb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for osiris board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for osiris board
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia30a7b915df14c91a2526dca3e374436da286b7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update override devicetree based on schematics.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2986ae6fd1f51efc6b9bb18ff2b7186357e55fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Configure GPIOs according to schematics.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8c4347fcc975ed994261c7738e5ef811a12e4b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Base on bernadino 14 adl-p 20220531.pdf, configure GPIOs
according to schematics.
GPP_B2 => BYPASS_DET
GPP_F19 => FP_USER_PRES_FP_L
BUG=b:234384954
TEST= USE="project_crota" emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ic2e7ecc34912f07463e0025787fdf59c7602e40b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch ensures google/volmar eMMC SKU has advanced PM support
enabled.
BUG=b:235915257
TEST=Able to boot to eMMC SKU to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e2883d894d2ca7f810f4b72af1c12037c8fdabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Adjust sensor trigger point and fan duty according to thermal team
tuning results.
BRANCH=brya
BUG=b:215033682
TEST=Built and tested on taniks board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I8135684d471fdcfdbbe2f1bc5455902d56bb71de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for volmar board
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I4d12f7214a306ded54b4536a27fe0fb7f3c33b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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There is an existing issue for nissa boards where wake up from
RTC wake is not working during suspend_stress_test.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Reference: https://review.coreboot.org/c/coreboot/+/64089
Later issue was found to be with GPP_F14 configuration for nissa
boards. When coreboot skips setting GPE_EN bit for GPP_F14, RTC
wake works properly. Another way to make it work is to skip locking
GPP_F14 GPIO to allow kernel to configure it properly.
This patch skips the locking for GPP_F14 to allow kernel to
configure it later. This fixes the issue of RTC wake not working.
Note: This patch provides workaround for the existing issue and
BUG will be closed once actual reason is identified and proper
fix is available.
BUG=b:234097956
BRANCH=None
TEST=RTC wake works on Nivviks board with the patch.
Change-Id: Ie8091ab8acf2b3f064cb79bdf4700f6b4c1674a5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add the support RAM parts for Xivu.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:236576117
BRANCH=None
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I02866f7dcdc70d1051d187fdda30e04bb654ece3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65252
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the xivu variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:235025984
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_XIVU
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I12341a2414e58ebc1c22429d35a03afef27adace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65235
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for MT62F512M32D2DR-031 WT:B and K3LKLKL0EM-MGCN.
These will be used as backup parts if there is issues getting the
Hynix parts.
BUG=b:233822880,b:236423310
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6ace8788ffb2ec40d01b91d0a4d751e0a95883f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Arbitrage is an internal tool at Google to work with schematics
programatically. In particular, it features an "export-coreboot-gpio"
command, which, does it's best to try and make a gpio.c from the
schematics to avoid human errors when translating to C code.
This commit adds a gpio.c generated by running:
"arb export-coreboot-gpio ghost4adl:P0_2022_06_17"
This GPIO config will require hand modification. This is done in a
follow-up CL. (i.e., this CL intentionally leaves the config exactly
how it was generated by Arbitrage so we get a good diff on the changes
we needed to make)
BUG=b:234626939,b:231719130
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I35a85202768a366357073d3ebc177d0e0da661f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65210
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initial boards will not have an internal panel. Enable TCSS display
detection so we can boot on an external panel over Type-C.
BUG=b:235294840
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6f65ddc24701d6f6ad0250560cc05b5e1d32370f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Based on 'commit 0b917bde36a7 ("mb/google/brya/var/kinox: Set power
limit based on charger type")' to refactoring update_power_limits
function for kinox.
BUG=b:231911918
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1fcb593090f95bf23808e577dd11b8a836f47494
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Adjust sensor trigger point and fan duty according to thermal team
tuning results.
BRANCH=brya
BUG=b:215033683
TEST=Built and tested on tarlo board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib543cee82f6940ab35a1a40af1d41bb2b8bf8521
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable PCIe WLAN for Kinox
1. Enable PCI port 5 for PCIe WLAN
2. Enable CLKREQ, CLK SRC 2 for PCI port 5
BUG=b:236175551
TEST=Build and boot to OS in Kinox. Ensure that the WLAN module is
enumerated in the output of lspci.
localhost ~ # lspci
02:00.0 Network controller: Realtek Semiconductor Co., Ltd.Device
c852 (rev 01)
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I3fbeadc85c9c88f5d178326dbbc83762083fe59a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65168
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Add Makefile.inc to include five generic LPDDR5 SPDs for the following
parts for Joxer:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:236576115
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I90acb436bccd5dae8585436316246c50fc256842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch adds a new CONFIG_VBOOT_GSCVD option that will be enabled by
default for TPM_GOOGLE_TI50 devices. It makes the build system run the
`futility gscvd` command to create a GSCVD (GSC verification data) which
signs the CBFS trust anchor (bootblock and GBB). In order for this to
work, boards will need to have an RO_GSCVD section in their FMAP, and
production boards should override the CONFIG_VBOOT_GSC_BOARD_ID option
with the correct ID for each variant.
BUG=b:229015103
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1cf86e90b2687e81edadcefa5a8826b02fbc8b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This patch ensures google/taeko eMMC SKU has advanced PM support
enabled.
BUG=b:235915257
TEST=Able to boot to eMMC SKU to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6b14130e47c3e3ec9b066456f3195841c83623a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65243
Reviewed-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures google/taniks eMMC SKU has advanced PM support
enabled.
BUG=b:235915257
TEST=Able to boot to eMMC SKU to ChromeOS.
Change-Id: I20c98006b6a45e2c8286480c560c8dbc0752327c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65213
Reviewed-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the pujjo variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Follow other ADLN variant to generate by manual)
BUG=b:235182560
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJO
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I73ec985bc19320260d0c3132c1ca23a3648df9e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nereid overridetree to enable port 10.
BUG=b:236162084
TEST=USE="project_nereid emerge-nissa coreboot" and verify it builds
without error.
Signed-off-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
Change-Id: Ic45301b863383e447b2dd3e06811b469cc247229
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65188
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for the MT53E2G32D4NQ-046 WT:C and MT53E512M32D1NP-046 WT:B
memory parts to skolas4es.
BUG=b:236284219
BRANCH=firmware-brya-14505.B
TEST=None
Change-Id: I5e3534985e12535ccc4285a0d829bca04781cf1b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65179
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The EEs and I misunderstood, and apparently the vfio-pci kernel driver
will turn off the dGPU when it sees it is unused, so coreboot should
leave the dGPU on so the kernel driver can save state before it shuts it
down.
TEST=Tested by ODM
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I30b5dead7a5302f3385ddcaecfbf134c3bb68779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65181
Reviewed-by: Robert Zieba <robertzieba@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Update PL1 and PL2 based on the suggestion of the thermal team.
Then the settings are both updated in firmware log.
BUG=b:233703656, b:233703655
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ibb81a1a8519b88ed4774385d9ccf895d64bbdc21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Create the joxer variant of the nissa reference board by copying
the template files to a new directory named for the variant.
BUG=b:236086879
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_JOXER
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4cb74f90c4ec33818b551d5f51759930e3222677
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
|
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Add pujjo supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K3LKBKB0BM-MGCP, K3LKCKC0BM-MGCP
2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6E
3. Micron MT62F512M32D2DR-031 WT:B
BUG=b:235765890
TEST=Use part_id_gen to generate related settings
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I929527a219452082e416803f7a74d470be5a188c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65100
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, the system fails to enter S0ix as the stop pin declation
for LAN device will prevent system from entering suspend.
So remove the stop pin declaration.
Also add device_index=0 for the first NIC to get correct MAC
from VPD setting.
BUG=b:210970640
TEST=Build and suspend_stress_test -c 20 pass
Check LAN works fine after resume
Change-Id: I513bf8b4bcb4d6db2eed2790fef7f6000a441274
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65123
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Add Elan touchscreen support for craaskvin.
BUG=b:235919755
TEST=Build and test on MB, touchscreen function works.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I18e0be688705942647c42ee532fcd32e862fe78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Add ALC5682I-VS related settings. And add codec/amplifier space in
fw_config.
BUG=b:229048361, b:235436515
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I567d3567318c810e19ae9e9ba5e0dc8332517866
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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Use fw_config Bit 5 to control whether to disable SD card:
Bit 5 = 0 --> enable SD card
Bit 5 = 1 --> disable SD card
BUG=b:229048361
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ib5e92600564e2138e32a0d2e60259b9767516a4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65129
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update gpio configuration based on GPIO_0610b.xlsx.
BUG=b:226182106, b:226182090
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I2b447629645690e5e97a17fff25860838f4f3344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
Different board versions have different audio layouts, therefore
support both layouts by enabling only the appropriate devices
in the devicetree via board_id().
BUG=b:207333035
BRANCH=none
TEST='FW_NAME=vell emerge-brya coreboot'
Change-Id: If053b8f85933f8fc75589ae175e225cc9c1e3991
Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65124
Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Some SKUs of crota have VNN 1.05v bypass rails for additional
power savings in S0ix states. This patch uses FW_CONFIG to enable
that feature when run on the applicable SKUs.
BUG=b:233175019
BRANCH=none
TEST=emerge-brya coreboot and verified pass
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Iaade50f4fe821b7114b3e2d44bda0747816da11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
enable_cnvi_ddr_rfim enables DDR RFI mitigation feature, this feature
needs to be enabled for all brya variants. Currently, it's not enabled
for brya4es.
BUG=b:201724512
TEST=Build, boot brya4es and check function 3 in _DSM method under
\_SB.PCI0.WFA3
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6cc9d3e4721188dcbc8584596c9f3f89a737206f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65110
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
- Set the speed to I2C_SPEED_FAST in each speed_config so that the
speed_config is actually applied. Currently, the speed_config isn't
applied, so the hcnt/lcnt calculation falls back to rise_time_ns and
fall_time_ns, which are 0 since they're not set. This results in
frequencies around 300 kHz.
- Move the data hold time to the speed_config, ensuring that the
resulting sda_hold value remains the same.
- For nivviks and nereid, tune scl_lcnt and scl_hcnt for each bus to
give a frequency around 390 kHz.
- In the baseboard, keep default scl_lcnt and scl_hcnt values. These
work well for buses with a rise time around 100 ns, and can be used as
a starting point before tuning them for a specific variant.
BUG=b:229547183
TEST=Measure the clock frequency, tHIGH, tLOW and tVD;DAT on nivviks
and nereid and check they meet the spec.
nereid clock frequencies:
I2C0 - 387.9 kHz
I2C1 - 392.7 kHz
I2C3 - 386.3 kHz
I2C5 - 383.6 kHz
nivviks clock frequencies:
I2C0 - 387.67 kHz
I2C1 - 380.47 kHz
I2C2 - 388.51 kHz
I2C3 - 384.03 kHz
I2C5 - 389.09 kHz
Change-Id: I88a6cfcc893183385eb85a89489e5d270277e537
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64942
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
A2 | | A0
C2 | | C0
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I8cc7be20988ff3cc3be1fac3c9b143059ff9190c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65088
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
change clk_src and clk_req to 4 for LAN_I225V based on
ADL_Moli_SC_MB_20220601.pdf.
BUG=b:235768639
TEST=emerge-brask coreboot and check LAN_I225V can connect.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I323726df84d07703402da9da44b1882a0cdc1e33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Remove the cnvi_bt_audio_offload because it is already probed in
variant.c for moli.
BUG=b:235426221
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I15077ca161b6283e764105d1c2fbc59ead1fd761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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enable use_custom_pld to match the custom physical location define.
BUG=b:235426221
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I62d133eed02faf4e5ad054a0901f73b1196c4c6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Won Chung <wonchung@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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The TBT device can't be recognized after we re-plug it at DB type-c
port. Intel found that tbt_pcie_rp0 has mapping error after each
re-plug. From Intel suggestion, we enable TBT PCIe RP0 to fix this
problem and take this as short term solution. Intel will implement
re-mapping mechanism in ACPI for long term solution.
BUG=b:230141802
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I61429033dfe64d67916167bb901bdd8246db953e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
BUG=b:229134437
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib0531ff736ed7ac52bff8607b26b3e7f1d3ac3ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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1. enable DDI_PORT_1, DDI_PORT_3 hot plug detection to let
tcp0 and tcp2 can display
2. remove DDI_ENABLE_DDC for Port 2, because tcp-dp dosen't need to
enable DDC
BUG=b:234521799
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I1354b82d881ebd838c310b32ae28ac2628ab8c9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable USB retimer in moli overridetree.
BUG=b:233869074
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ib7ea0b0d85776857d07e129935059397720fa0e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
mainboard_vbt_filename() is to decide which VBT to return,
but moli only has one VBT, so it doesn't need this function.
BUG=b:234521809
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia9c1495c8cb7bf7b47d9c616891a791a32b9d805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64848
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create new variant of Brya "ghost4adl".
Memory config and device tree was sourced from the schematics
(revision 7670d041f40279b5126990f20ec8f90c0538440c).
GPIO overrides have not been added yet. This is to be added in a
follow-on CL.
BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Override the type-C USB2 port setting from `USB2_PORT_TYPE_C` to `USB2_PORT_MAX_TYPE_C`.
The change is required to detect USB2 device on type-C port of Agah boards.
BUG=b:233554817
TEST=build and test USB2 hub could be detected on both the Type-C ports.
=================================================================
usb 3-3: New USB device found,idVendor=1a40,idProduct=0801,bcdDevice= 1.00
usb 3-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0
usb 3-3: Product: USB 2.0 Hub
hub 3-3:1.0: USB hub found
hub 3-3:1.0: 4 ports detected
=================================================================
Change-Id: I856402aa128db0c4ba092e1c2a66e29bc9165c40
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64988
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add craaskbowl supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K3LKBKB0BM-MGCP
2. Hynix H9JCNNNCP3MLYR-N6E
BUG=b:235134420
TEST=Use part_id_gen to generate related settings
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64858
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a mem_parts_used.txt, generate Makefile.inc and
dram_id.generated.txt for this part.
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
H9JCNNNCP3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 2 (0010)
K3LKLKL0EM-MGCN 3 (0011)
H58G56AK6BX069 2 (0010)
BUG=b:233830713
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: If9f2b65717a05576fa6b4fb1f53133902ff1a7c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64982
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C3 | | C0
C2 | | C1
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I2153f826d7ff05f42935f08d5d1f5127ac944575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64728
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch uses ACPI _PLD macros to add custom values for USB ports.
C2 C0 A3 A2
+----------------+
| REAR |
| |
| |
| |
| FRONT |
+----------------+
C1 A1 A0
BUG=b:232298007
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I6a9ead24ef9d73bc0b09301cf641009ced0c6810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64732
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
add fw_config probe for auido and enable BT offload support.
BUG=b:232419816 b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id58e48cc2510d0377040d86bb9dbbb45bec7d624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update override devicetree based on schematics.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Based on latest schematic to update the gpio table.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Remove EEPROM power source interconnect with camera power on/off
and keep it always on.
There appears to be a rare case where the camera EEPROM is not
able to be read from. As a workaround, this patch leaves the
EEPROM power rail on in S0.
BUG=b:229049914
TEST=tested the changes with redrix 5MP(ov5675/hi556) camera.
Change-Id: I9efab9bb65632a73c1c2635729c38a2aa14c69b2
Signed-off-by: Arec Kao <arec.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The _DSM subfunction for the Nvidia GN20 supports 1 additional
subfunction, known as GPS, which is required to support GPU Boost. This
implementation is minimal, essentially letting the GPU manage its own
temperature.
BUG=b:214581372
TEST=abuild
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I21331bd811a13212f3825bda44be44d1b5ae7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that the power sequencing for the GPU is in a better shape, ensure
that the ACPI code that performs power sequencing matches the C code
that does the same.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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During the GPU power down sequence, each power rail should reach below
at least 10% before the next rail is sequenced down; based on scope
shots for a board, conservative delays between each rail are added;
they will likely be more fine-tuned later on.
BUG=b:233959099
TEST=sequence verified by EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I28ada3a01b86996e9c7802f8bd18b9acda6bb343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add OVTI8856 information for craask
BUG=b:232656913
TEST=Build and boot on craask
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ice490f31e9ab8fffff6a7a5d24f769efea91188d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add the support LP5 RAM parts for vell:
DRAM Part Name ID to assign Vendor
H58G56AK6BX069 2 (0010) Hynix
BUG=b:227595062
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: Ibe09285c15b28ceeb6ab0d6c94f90e00584ac07d
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The Nvidia GPU kernel driver supports another _DSM subfunction which
is known as NVPCF (Nvidia Platform and Control Framework). The
subfunction informs the kernel driver about Dynamic Boost parameters,
which is done at init time, but can also be changed dynamically.
BUG=b:214581372
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7887bfc2e8e1cae606e12502a9eda3a7954c8d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Set different power limit values using host command to detect charger
type from ec.
Scenario:
1. With 90W customized adapter, set to baseline.
2. With 170W customized adapter, set to performance.
3. With above 90W barrel jack/type-c adapter, set to performance.
4. With below 90W barrel jack/type-c adapter, set to baseline.
BUG=b:231911918
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9c8a5a7de8249e61468e277ec55348b660253c5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Follow GPIO_Table_0527.xlsx to update gpio configuration.
- Set GPP_A15 to NC.
- Set GPP_A20 to TCP_DP1_HPD (native function1).
BUG=b:225384873
TEST=Build and boot to Chrome OS.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1c7a211c3bef1f1fe4f94345186c33363a90e11f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Follow thermal table from thermal team.
Chang list:
1. Update TEMP_PCT of Active Policy for TSR1.
BUG=b:230829301
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Nereid
BUG=b:233030505
BRANCH=None
TEST=Build FW and test on Nereid board.
Verified thermal throttling successfully when participant reaches temp
threshold as per Passive Policy.
Also, verified system shutdown when Temperature of participants are
reaching threshold as per Critical policy.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: I195f4b507ee57948751f0119735d8350dfce984b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
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This patch configures external V1p05/Vnn/VnnSx rails for Craask
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:233717182
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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In order to enable the UFS controller (PCI device 12.7), the PCI
specification says that the device at function 0 in the same slot must
also be enabled, which is the ISH. Therefore, enable ISH when UFS is
present.
For more context on why this is necessary, see CB:62662 which enabled
UFS and ISH for adlrvp_n.
BUG=b:234136500
TEST=Build test. Will test that UFS works once we have hardware.
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: Ib60d44322cfbd8f82c33ecac7598881dfb1d0c3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Daniil Lunev <dlunev@chromium.org>
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This commit adds the skolas baseboard, which is basically the brya
baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder
Lake SoC.
This commit also adds the skolas baseboard variant skolas4es.
Since this baseboard is identical to the brya baseboard with the
exception of the SoC used, the new baseboard and the new baseboard's
first variant will be a copy of the current brya baseboard and brya0
variant.
For now, the skolas baseboard and skolas4es variant will continue to
use ADL-P. This allows for two benefits:
1. software to be proven out on existing hardware prior to RPL SoC
support landing, and
2. allows us not to have to wait for RPL SoC changes prior to getting
the mainboard changes in place
Once the RPL SoC code has merged, I will update the skolas baseboard and
skolas4es variant to use RPL instead of ADL.
BUG=b:229134437
TEST=util/abuild/abuild -p none -t google/brya -x -a -c max
Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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All Osiris SKUs use the new RGB gaming keyboard,
so don't need the fw_config to decide keyboard matrix.
BUG=b:220800586
TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19211c345de0b315d65ec64efc70826e81315810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Craask uses CNVi WLAN, so disable the PCIe-related GPIOs.
BUG=b:229040345
Test=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I7bcf041503dcee448758dac46b1c9711d0b02ba3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
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BUG=b:210970640
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I90d9f2e298e54832bc077eae1c8be0e39c151d90
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Starting with id 2, boards switched the memory SMBus slave address, and
use 0x50, 0x52.
BUG=b:233975373
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I5e683ffdbc0727259ee796610cd97a6e378bf335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
A0 | MLB DB | A1
| |
+----------------+
BUG=b:232256907
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia288937ef3a4229088b60d87d31ea88057377a71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
A0 | MLB DB | A1
| |
+----------------+
BUG=b:232256907
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: If2a77c0239646759e0192b72ba1991d334dd15aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
A0 | MLB DB | A1
| |
+----------------+
BUG=b:232256907
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I47b069377046652ba4d278733a15bbca98bdb739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.
We checked power on sequence requires enable pin prior to reset pin
delay of 50ms and add delay of 20ms to meet the sequence on various
eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in
chapter 7.2.
BUG=b:232327947
TEST=Build and suspend_stress_test -c 2500 pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
K3LKLKL0EM-MGCN
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ie022dd95929549ddd403d4c1d1c52174fd3fd721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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Select vbt bin files based on DB_DISPLAY field of FW_CONFIG.
BUG=b:233690293
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Idb92be66927259732bfd27e4db2c9f242da7d200
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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In order to meet the OEM's acoustic specifications, the pre-wake
randomization time (DPA) is set to 100.
BUG=b:228410327
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Idaf3f931a2c0f2373445948e5f53a82328ec7ba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Future nissa devices will mostly use 16MB SPI flash. Add 16MB layout and
make it default for nissa.
BUG=b:202783191
TEST=build nissa and brya firmware, check they're still 32MB
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I04ae46d62d3e018610ca2533c186dda980bd67bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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To support speaker AMP CS35L53-CWZR'S I2C needs to split to two
I2C ports
BUG=b:207333035
BRANCH=none
TEST=built and verified speaker
Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com>
Change-Id: I8095abc4fc3233b21b818a508c84cd59b39fc1d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
|
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This reverts commit bd9cec8ae5755e898d107fd061fc2e2f983552b9.
Reason for revert: Enable i2c7 for amp changing to 2 channel
because vell setting amp on i2c0 and i2c7 on next phase
BUG=b:229334701
TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend
&& checks EC log and ensures the DUT could enter s0ix.
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Change-Id: I5988cd9926b2c9ced1d111774abaa897bef91537
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Kinox has four temperature sensors. Modify the target of DPTF active
policy to map correct temperature sensor.
BUG=b:231380286
TEST=Boot to Chrome OS and doesn't see "DPTF: Invalid sensor ID" from ec
comsole.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Icb5c285a6f483e2a1b6510a962ff7f7f6e9a79e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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The dGPU used for some Brya projects requests 32 bits of address space
for one of its BARs via the Resizable BAR mechanism. This Kconfig is
currently set at 29 bits for brya, so the allocation currently is
capped at 29 bits. This patch sets the limit to 32 bits for brya
boards, which is enough for the GPU.
BUG=b:214443809
TEST=all of the dGPU PCI BARs on agah can be successfully allocated
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I61dbe47f1f316967d052bae748ff23babde61ef0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
|
