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path: root/src/mainboard/google/brya/variants
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2024-10-07mb/google/brya/var/glassway: Add audio codec ALC5650Daniel_Peng
1.Add AUDIO fw_config setting. 2.Add audio codec ALC5650 related settings for Gallida360 project. BUG=b:364798053 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I3761ca6d4cad18c74f5e1a056f0cb465dc4ac3ea Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-30mb/google/brya/var/bujia: Add Wifi SAR for bujiaShon
Add wifi sar for bujia. BUG=b:345364452 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I5a67f3723a9dc33793a5cd95f9a3a2596c3c1fc6 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84501 Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-09-30mb/google/nissa/var/riven: Add 2 memory parts and generate DRAM IDsDavid Wu
Add two new memory parts 1. K3KL8L80CM-MGCT (Samsung) 2. H58G56BK8BX068 (Hynix) BUG=None TEST=Run part_id_gen tool and check the generated files. Change-Id: I557b359d9e639f6c3fac4239eb28aa7e0bed4c0e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-26mb/google/{nissa,trulo}: Add Vccin Aux Imon Iccmax default valueSimon Yang
Add default value in nissa and trulo devicetree.cb, ODM have to review the board design to follow RDC#646929 Power Map requirement. NOTE: The VccInAuxImonIccImax remains unchanged w/ and w/o this CL. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST='emerge-nissa coreboot chromeos-bootimage' Change-Id: Iaedd34757aa6802edcae402e751bc39b9cfe9e0c Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83725 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-24mb/google/brya/var/vell: Disable I2C6 controllerSubrata Banik
This patch disables unused I2C6 controller for the 'vell' variant of the 'brya' mainboard. BUG=b:352330495 TEST=Able to build and boot google/vell. Change-Id: I5b39e44bb64bf2285c962249c0d94a8d5325f0c7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-23mb/google/nissa/var/nivviks: Update the power resource for NVM and VCMSowmya V
Earlier change (https://review.coreboot.org/c/coreboot/+/84019) pushed to resolve the privacy LED blinking issue regressed the camera autofocus functionality. This change updates the power resource for NVM and VCM in line with the tivviks schematics to fix the issue. BUG=b:365899407 TEST=Build and boot tivviks. Verified the Autofocus and all the camera basic sanity tests. Change-Id: Id3e256d59982ac176844e289f18ee450079704b9 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-19mb/google/nissa/var/riven: enable WIFI SARDavid Wu
According to the CL:chrome-internal:7651905, Riven will use the fw_config to separate SAR setting. CNVI + ID_0 --> wifi_sar_0.hex for WIFI6 PCIE + ID_1 --> wifi_sar_9.hex for WIFI7 BUG=b:366060274 TEST=build, enabled iwlwifi debug, and check dmesg as below. iwl_sar_fill_table Chain[0]: iwl_sar_fill_table Band[0] = 132 * .125dBm iwl_sar_fill_table Band[1] = 136 * .125dBm iwl_sar_fill_table Band[2] = 136 * .125dBm iwl_sar_fill_table Band[3] = 136 * .125dBm iwl_sar_fill_table Band[4] = 136 * .125dBm iwl_sar_fill_table Band[5] = 144 * .125dBm iwl_sar_fill_table Band[6] = 144 * .125dBm iwl_sar_fill_table Band[7] = 144 * .125dBm iwl_sar_fill_table Band[8] = 144 * .125dBm iwl_sar_fill_table Band[9] = 144 * .125dBm iwl_sar_fill_table Band[10] = 144 * .125dBm iwl_sar_fill_table Chain[1]: iwl_sar_fill_table Band[0] = 132 * .125dBm iwl_sar_fill_table Band[1] = 136 * .125dBm iwl_sar_fill_table Band[2] = 136 * .125dBm iwl_sar_fill_table Band[3] = 136 * .125dBm iwl_sar_fill_table Band[4] = 136 * .125dBm iwl_sar_fill_table Band[5] = 144 * .125dBm iwl_sar_fill_table Band[6] = 144 * .125dBm iwl_sar_fill_table Band[7] = 144 * .125dBm iwl_sar_fill_table Band[8] = 144 * .125dBm iwl_sar_fill_table Band[9] = 144 * .125dBm iwl_sar_fill_table Band[10] = 144 * .125dBm Cq-Depend: chrome-internal:7651905 Change-Id: I647d64a008991a7a20791b2c87ea6308af6bb82e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84339 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-17mb/google/brya/var/trulo: Update ISH GPIO config for tablet mode switchVarun Upadhyay
This patch configures the GPIO pins for ISH to notify EC about the tablet mode change in accordance with schematic_20240607. BUG=b:347811875 TEST=Build and boot google/trulo. Placed the device in tabletmode & on EC console,"tabletmode" command shows "tablet mode". Change-Id: Id22e397e46b522428ffdabe34a445ed7e4fb6fc5 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-13mb/google/brask/var/bujia: Fix PSYS voltage settingShon
It return 0 when google_chromeec_command() on success, so get_input_power_voltage() should return adaptor voltage instead of psys_config default value. BUG=b:329037849 BRANCH=firmware-brya-14505.B TEST= cbmem -c | grep -i PsysPmax Change-Id: I848c92752b7a7b53f47c6296aad0bdda20e9b0bd Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84333 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/google/nissa/var/teliks: Update eMMC DLL tuning valueszengqinghong
Update eMMC DLL tuning values for improved initialization reliability. BUG=b:361013271 TEST=Cold reboot stress test over 2500 cycles Change-Id: Icd1f9c7bdec2bc99152a13ac4ce0724a26718a52 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84248 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10mb/google/nissa/var/joxer: Use `DB_USB` to probe conn1 deviceSubrata Banik
Joxer experienced error messages during developer mode entry due to failed USB-C1 probing. This patch adds the `DB_USB DB_1C` probe directive to the `conn1` device in the overridetree, ensuring USB-C1 is only probed when `FW_CONFIG` supports the applicable hardware SKU. This should resolve the error flood seen during dev mode entry on Joxer. BUG=b:364240631 TEST=Able to build and boot google/joxer to OS without any error. w/o this patch: send_packet: CrosEC result code 9 send_packet: CrosEC result code 3 Failed to get PD_MUX_INFO port1 ret:-3 update_all_tcss_ports_states: port C1: get_usb_pd_mux_info failed send_packet: CrosEC result code 9 send_packet: CrosEC result code 3 Failed to get PD_MUX_INFO port1 ret:-3 w/ this patch: No error reported during dev mode entry Change-Id: I8cdefa01409d5a8a75032f30dacde40057e064dd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-06mb/google/brask/var/bujia: Add PSYS settingShon
According to the Intel OPS spec, the DC power from display is 12~19V@8A max. It can't set PsysPmax by unknown voltage, so get voltage by ec command "ectool adcread 4" then calculate PsysPmax value. The OPS display can supply 90W power, configure psys_pl2 to limit the system power to 90W. BUG=b:329037849 BRANCH=firmware-brya-14505.B TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk intel-rplfsp intel-adlfsp coreboot chromeos-bootimage Check adcread value by ectool adcread 4. If get 19540, PsysPmax should be 19540 * 8000 ~= 156 W. Check FSP debug log have the following message. PsysPmax = 156W Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-09-06mb/google/nissa/var/yavilla: Add 1.2V enable pin in VCMWisley Chen
Add control for the 1.2V enable pin in VCM to comply the mipi camera power sequence. 2.8V enable --> 1.2V enable --> reset BUG=b:362386165 TEST=Run ITS test Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84211 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-05mb/google/nissa/var/riven: Update GPIO pins for 3rd dmic supportDavid Wu
When world-facing camera is absent, coreboot need to enable GPP_R6(DMIC_WCAM_CLK) and GPP_R7(DMIC_WCAM_DATA) for 3rd dmic support BUG=b:333973512 TEST=Boot google/riven to OS and verify 3rd dmic working properly. Change-Id: I6c8780ce37b5d3987f5cdf6e6e6d0b4896b33230 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84141 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-04tree: Use boolean for emmc_enable_hs400_modeElyes Haouas
Change-Id: I41a877ed7f5f3d02904dc939b32996a7f6d45373 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for disable_package_c_state_demotionElyes Haouas
Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04tree: Use boolean for disable_c1_state_auto_demotionElyes Haouas
Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-02mb/google/nissa/var/teliks: Add fw_config fields for rtl8852becengjianeng
Add a new fw config field for wifi category as WIFI_6_8852, which is PCIe based. Also, enable WIFI_6_8852 for existing PCIe based wifi port as well as bluetooth port. BUG=b:356434907 BRANCH=NONE TEST=Verified Wifi6 module detection Change-Id: Ib6ba641c23cce7f1253022c9bb78b986b323bcaa Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84138 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02mb/google/nissa/var/teliks: Force audio mute to avoid screen flickcengjianeng
Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, it is because it inserts 12 blank frames if it receives the unmute in VB-ID. Always override the mute in VB-ID to avoid Tcon EC detected the audiomute_flag change. BUG=b:360243615 BRANCH=firmware-nissa-15217.B TEST:Verfied on Teliks and cannot reproduce the issue Change-Id: Iff488f6844c717ef24069c7176e7b8dfb07d8abc Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84137 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
2024-09-02mb/google/brya: Add romstage early graphics for trulo baseboardSubrata Banik
1) Add all required changes for eSOL support. 2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo. The CSOT (MNC207QS1-1) panel is used for the devicetree. BUG=b:362895813 TEST=On-screen text message seen during MRC training on Trulo SKU1. MRC: no data in 'RW_MRC_CACHE' bootmode is set to: 0 DP PHY mode status not complete DP PHY mode status not complete DP PHY mode status not complete ... Informing user on-display of memory training Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84128 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2024-09-01tree: Use boolean for s0ix_enableElyes Haouas
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-29mb/google/brya/var/nova: Configure scaler I2C GPIOsKenneth Chan
According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL). BUG=b:358439747 TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C. Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-28mb/google/nissa/var/anraggar: Force audio mute to avoid screen flickSimon Yang
Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, it is because it inserts 12 blank frames if it receives the unmute in VB-ID. Always override the mute in VB-ID to avoid Tcon EC detected the audiomute_flag change. BUG:b=357764688 BRANCH=firmware-nissa-15217.B TEST:Verfied on Anraggar and cannot reproduce the issue Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-28mb/google/nissa/var/nivviks: Prevent camera LED blinking during bootSowmya V
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. TEST=Build and boot nivviks. Monitor the camera LED blinking during boot. Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-25Revert "mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT"Seunghwan Kim
This reverts commit aa6865291a7ddfae4c67fcfc55ebd0c13a376807. Reason for revert: We applied this patch for touchpad stuttering issue for XOl, but the same touchpad problem was reported. So we would revert this change and apply kernel patch (crrev/c/5808335) to avoid the touchpad issue. Change-Id: I78139932e76dbd4128fb325dd70b7dcff3bcc81c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-24mb/google/nissa/var/nivviks: enable WIFI_SARDavid Wu
Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG for WIFI_CATEGORY to choose the right wifi_sar hex file. Below is the file mapping: wifi_sar_0.hex = wifi6 wifi_sar_1.hex = wifi7 BUG=b:345596420 TEST=emerge-nissa coreboot chromeos-bootimage Cq-Depend: chrome-internal:7607427 Change-Id: If8339a2a1d32d3e885ef87ea2ec2847f107f1fbd Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84051 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23mb/google/nissa/var/riven: Set VccIn Aux Imon IccMax to 25ADavid Wu
Iccmax of VccIn_Aux is 25A with MBVR design. BUG=b:348258637 TEST=Local build successfully and boot to OS normally. Change-Id: I59c420c03a8f01d185f616a2212798266b4251e0 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-08-23mb/google/nissa/var/sundance: Adjust GPIO GPP_C1 to no_pull-upRoger Wang
EE change GPP_C1 from pull-up to OD&no pull-up in PCH GPIO Table. BUG=b:358472598 TEST=Build and verified test result by EE team Change-Id: I84d1b42a39bebbcd610cebc46f979018fc79238f Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83904 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-23mb/google/nissa/var/nivviks: Correct USB port for PCIE WLAN bluetoothDavid Wu
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN bluetooth companion device. BUG=b:345596420 TEST=Build and test on nivviks, check BRDS is shown in SSDT. Change-Id: I0908ff500434401bf89a5313427cf304f32cf929 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-08-23mb/google/nissa/var/riven: Correct USB port for PCIE WLAN bluetoothDavid Wu
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN bluetooth companion device. BUG=b:345596420 TEST=Build and test on revin, check BRDS is shown in SSDT. Change-Id: Ie8174567b863e1afe8b0a27e644e24e9d3de6d19 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84020 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-22mb/google/nissa/var/teliks: Adjust usb2 pin of wlanzengqinghong
Since the voltage value measured by the USB2 pin of the wlan is 500mv, it does not meet the design requirements. Adjusting the port length can reduce the voltage to 450mv, which meets the expected settings. BUG=b:361037189 TEST=1. The voltage measurements are as expected. 2. The Bluetooth and WiFi functions of the wlan module are verified to be normal. Change-Id: Icd1ec3b561ee5b3f55e5f97a56fd9cb7df893508 Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-08-21mb/google/byra/var/kinox: Add/update VBT filesMatt DeVillier
Kinox has two VBT options, selected via fw_config. Add the second option to CBFS, and update the original file. Extracted from Google_Kinox.14505.704.0.bin. TEST=build/boot kinix, verify firmware display init successful and payload menu visible. Verify correct VBT selected via cbmem log. Change-Id: I01c19222628fee3874ef592ec40b40d9bd679dce Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83996 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-21mb/goog/brya: unlock gpio wake sourcesNick Vaccaro
The power off code in depthcharge disables all GPEs prior to power off. The problem is that for gpio wake sources that are locked, this power off code cannot successfully clear any pending interrupt from that source. This can result in the device incorrectly waking back up after it's been powered off from the firmware dev screen. BUG=b:360380950, b:359692570 BRANCH=firmware-brya-14505.B TEST=verify brask, nissa, or brya DUT is able to power down and stay powered down when selecting the "Power off" button in the firmware dev screen. Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-20mb/google/nissa/var/riven: Set PCIE WLAN bluetooth companion deviceSubrata Banik
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:345596420 TEST=Build and test on revin, check BRDS is shown in SSDT. Change-Id: I87cfbdd0b8a97d84a96af373855219c60f39f173 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-20mb/google/nissa/var/nivviks: Set PCIE WLAN bluetooth companion deviceSubrata Banik
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:345596420 TEST=Build and test on nivviks, check BRDS is shown in SSDT. Change-Id: Ib654f22033c68edbc602f14537aaa2151800598d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83943 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19mb/google/brya/var/nova: Set up soundbar-related GPIOsKenneth Chan
Set up soundbar-related GPIOs for updating. BUG=b:358435383 TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I517da8de90487533e49e46649c5acf4ccfcc5160 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83936 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-19mb/google/nissa/var/sundance: Adjust WWAN GPIO sequenceRoger Wang
This patch removes WWAN configuration from the bootblock. It appears that setting it up in the bootblock may not be necessary. Configure in bootblock,the seq will be triggered at the same time. The customer would like us to leave some buffer for EN to RST. BUG=b:357764679 TEST=Build and verified test result by EE team Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83792 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-15mb/goog/brya: Don't lock GPP_F15 (FPMCU_INT_L)Nick Vaccaro
Locking GPP_F15 causes DUTs with fingerprint sensor to not be able to correctly power down and stay powered down. This pin does not need to be locked. BUG=b:359692570, b:356750516 BRANCH=firmware-brya-14505.B TEST=`FW_NAME=gimble emerge-brya coreboot chromeos-bootimage`, flash and boot gimble into developer mode, then reboot into dev screen and select the "Power off" button and verify gimble powers off and does not power itself back up. Change-Id: I1c73035b02021b0d1268cd46dcd0841621556ad5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83932 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-14mb/google/nissa/var/riven: Disable external fivrDavid Wu
In next phase, riven will remove external fivr. Use the board version to config external fivr for backward compatibility and show message. BUG=b:359062365 TEST=build, boot to OS, suspend/resume work normally. Change-Id: Id5f538b2eda7820a922b8d9ee14b2bae7df3726c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-13mb/google/brya/var/nova: Enable TCSS XHCI settingPranava Y N
This patch enables the TCSS XHCI in the devicetree to solve the genesys hub enumeration issue. BUG=b:348332200 TEST=Able to build google/nova and ensure lsusb can list genesys hub device. Change-Id: Ic8e25756a2975e884434c4c7e3d587f4c1f0ed0b Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83845 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13mb/google/nissa/var/pujjoga: Modify GPP_C1 settingLeo Chou
Confirm with EE, the GPP_C1 don't need PU 20K. So modify GPP_C1 setting to remove PU 20k Schematic version: 500E_GEN4S_ADL_N_MB_0418 BUG=b:358162951 TEST=Build and boot on pujjoga. Change-Id: I7ad16cd29ab467d3eac74dab40522c577d91c747 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83818 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-13mb/google/nissa/var/pujjoga: Modify P sensor settingLeo Chou
1. The P sensor need follow WWAN FW_CONFIG to enable/disable 2. Modify GPP_H19 setting to PAD_CFG_GPI_APIC to fix PLT test fail Schematic version: 500E_GEN4S_ADL_N_MB_0418 BUG=b:357998089 TEST=1. Boot to OS and verify the P sensor devices is set based on fw_config. 2. Confirm that the PLT test can pass successfully. Change-Id: Ic3610180c8cf99eba9367e26bfc3666410af19f7 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-13mb/google/nissa/var/riven: Add elan touchscreen supportDavid Wu
This change adds the necessary configuration for the elan touchscreen (ELAN9004) device, connected to I2C bus 16. It includes settings for: * HID descriptor * Device description * IRQ configuration * Detection * Reset, stop and enable GPIOs with their respective delays * Power resource handling * HID descriptor register offset BUG=b:348125053 b:348126380 TEST=emerge-nissa coreboot boot with elan TS, make sure elan TS is functional. Change-Id: I64c5a11dfaacfcca34240375d4dca5c76a60f62e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83876 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-11mb/google/nissa/var/teliks: Add DP AUX BIAS connectzengqinghong
Because one side is not displayed when using type-c projection, the configuration of DP AUX BIAS to SOC direct connection is added. BUG=b:352263941 TEST=DP function of MB and DB workable Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83829 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-11mb/google/brya/variants: Enable pch_hda_sdi_enable for trulo baseboardDinesh Gehlot
This patch enables pch_hda_sdi_enable for the trulo baseboard and removes SDI lanes update from its variants. BUG=b:350931954 TEST=Boot verified on google/craask and google/tivviks Change-Id: I2e0f43b8fffb5e583089769d2c7446b476ce5d5d Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83859 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09mb/google/nissa/var/riven: Add G2 touchscreen supportDavid Wu
This change adds the necessary configuration for the G2 Touchscreen(GTCH7503) device, connected to I2C bus 40. It includes settings for: * HID descriptor * Device description * IRQ configuration * Detection * Reset and enable GPIOs with their respective delays * Power resource handling * HID descriptor register offset BUG=b:350844195 TEST=emerge-nissa coreboot boot with G2 TS, make sure G2 TS is functional. Change-Id: If17367cd62eb69a1237efe4aa3ca1a0c9640ba4c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83823 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-09mb/google/trulo: Enable EC MKBP deviceAmanda Huang
MKBP device is required for passing events from input sources to AP. Input sources include buttons (power, volume); switches (lid, tablet mode) and sysrq. BUG=b:357521411 TEST=Build coreboot and switch tablet mode on orisa. Change-Id: Ic712f53fb4063347c38df05167f0100afc06f979 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83819 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-08mb/google/brya/var/trulo: Update ISH GPIO's configurationVarun Upadhyay
This patch configures the GPIO pins to enable ISH on the Trulo device, in accordance with schematic_20240607. BUG=b:354607924 TEST=Builds successfully for google/trulo. Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83781 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-08mb/google/brya/var/orisa: Update ISH GPIO's configurationVarun Upadhyay
This patch configures the GPIO pins to enable ISH on the Orisa device, in accordance with schematic_20240607. BUG=b:354607924 TEST=Builds successfully for google/orisa. Change-Id: I24745ba629c59c092ce676b29915e356a4d8d8af Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83656 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-08-06mb/google/trulo: Register Firmware name for ISHVarun Upadhyay
Define ISH main firmware name so ISH shim loader can load firmware from file system. BUG=b:354607924 TEST=Boot trulo board, check that ISH is enabled and loaded lspci shows: 00:12.0 Serial controller: Intel Corporation Device 54fc Change-Id: Id60cb416a1cce5407bd483f0ce54f477584459b1 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83671 Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-04mb/google/brya/var/nova: Adjust Type-C port to USB 2.0 onlyPranava Y N
This patch introduces the following changes, - Remove TCSS XHCI (USB 3.x) devicetree settings - Update Over Current (OC) & USB 2.0 config - Update TCSS-XHCI capabilities BUG=b:348332200 TEST=Able to build google/nova and ensure lsusb can list genesys hub device. Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83707 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-04mb/google/brya/var/nova: Remove PMC MUX settingPranava Y N
This patch removes the PMC MUX related setting from devicetree as Nova doesn't include a MUX for it's USB-C port. BUG=b:348332200 TEST=Able to build google/nova Change-Id: I23a949ba9b598d7a86c6f8b08a2821651978e489 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-02mb/google/brya/var/trulo: Remove mux references from typec portAmanda Huang
The Type-C kernel driver no longer programs the AP mux. So remove device references to the TCSS Mux control device from the Type-C port driver. BUG=b:351117685 TEST=USB-C drive can be detected after system warm or cold reboot. Change-Id: I2fd6e8fcebd194da03ba3f264ee89037ca11769a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83746 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-08-01mb/google/nissa: Create teliks variantzengqinghong
Create the teliks variant of the nissa reference board by copying the anraggar files to a new directory named for the variant. BUG=b:352263941 BRANCH=None TEST=1. util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TELIKS 2. Run part_id_gen tool without any errors Change-Id: I744f4d7c2d35544d3a8a8f76e24bad3298442768 Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83408 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-01mb/google/brya/var/orisa: Remove mux references from typec portAmanda Huang
The Type-C kernel driver no longer programs the AP mux. So remove device references to the TCSS Mux control device from the Type-C port driver. BUG=b:351117685 TEST=USB-C drive can be detected after system warm or cold reboot. Change-Id: I4a24fb69ebec87f65b679cde0e4a1a8827cd365d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83722 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-31mb/google/trulo: Keep ISH default enableSubrata Banik
This patch drops fw_config probing for ISH because ISH IP should remains on by default for all Trulo variants. Additionally, removed the redundant ISH entries from variant override devicetree. BUG=b:354607924 TEST=Able to verify ISH PCI Device is available while booting eMMC sku. ``` lspci 00:00.0 Host bridge: Intel Corporation Device 461c ... 00:12.0 Serial controller: Intel Corporation Device 54fc ... 00:1a.0 SD Host controller: Intel Corporation Device 54c4 ``` Also, able to enter S0ix with this patch. ``` > suspend_stress_test -c 1 --ignore_s0ix_substates At AP console: s0ix errors: 0 s0ix substate errors: 0 s0ix pc10 errors: 0 At EC console: power state 5 = S0ix, in 0x38d87 ``` Change-Id: Ic1e415ec848ac91a9bbf21b26597f4e6b5f7a1f5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83695 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-31mb/google/brya/var/xol: Using baseboard's PchPmSlpAMinAssert settingsRaymond Chung
Reduce PchPmSlpAMinAssert (pch_slp_a_min_assertion_width) to minimum time (98ms) from 2sec. BUG=b:349595391 BRANCH=firmware-brya-14505.B Test=Verified on xol Change-Id: Ia4b7b7ab5dc9afeb3505dfd2b42d0d397aed7a5c Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83683 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-30mb/google/brya/var/orisa: Remove redundant defaults from overridetreeRishika Raj
Streamline variant-level overrides by removing redundant entries that already exist in either the SoC-level or the platform-level configurations. BUG=None TEST=emerge-nissa coreboot Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27mb/google/brya/var/trulo: Add USB2 Bluetooth device on Port 10Subrata Banik
This change adds a new USB2 Bluetooth device configuration on Port 10 for the Trulo variant. * A new `drivers/usb/acpi` chip is added with: * `desc` set to "USB2 Bluetooth" * `type` set to "UPC_TYPE_INTERNAL" * `reset_gpio` set to "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" * `device` referencing `usb2_port10` BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I9a92a4d008eb4d0c339079ecbbb77facece435ba Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-27mb/google/brya/var/trulo: Remove unused Bluetooth deviceSubrata Banik
This change removes the configuration for the unused USB2 Port 6 (index 5) and its associated Bluetooth device on the Trulo variant. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I9970274b9b1b1076a2f9d649d61c825cac71d0c7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83665 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rishika Raj <rishikaraj@google.com>
2024-07-27mb/google/brya/var/orisa: Remove unused Bluetooth deviceSubrata Banik
This change removes the configuration for the unused USB2 Port 6 (index 5) and its associated Bluetooth device on the Orisa variant. It also cleans up a redundant newline before the `serial_io_i2c_mode` definition. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: Icf1ff442530ad2263ad0b58829e5c7b2ce544439 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83664 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rishika Raj <rishikaraj@google.com>
2024-07-27mb/google/brya: USB2 Port 9 for integrated BT on Trulo baseboardSubrata Banik
This patch moves the configuration for integrated Bluetooth functionality (USB2 Port 9) from Orisa variant to the Trulo baseboard. This change is necessary to support the CNVi BT module on Trulo variants. The configuration is skipped for Orisa. Trulo: USB2 Port 9 is now configured as USB2_PORT_MID(OC_SKIP) to support the CNVi BT module. Orisa: The previous configuration of USB2 Port 9 as a Bluetooth port for CNVi WLAN has been removed. This change ensures proper Bluetooth connectivity is applicable for all Trulo variants including Orisa and Trulo. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83663 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-27mb/google/brya/var/orisa: Update fw_config probe for storage devicesRishika Raj
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices. 2. Update fw_config probe to enable/disable devices in devicetree. 3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config is enabled. BUG=None TEST=emerge-nissa coreboot Change-Id: Id3a22aa2206e86fdca6f6fadbc849572890fee58 Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83657 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-25mb/google/brya/var/trulo: Configure GPIO pins for ramstageSubrata Banik
This patch configures GPIO pins as required for booting the Trulo device from ramstage. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I7b540416083a923ba4d2e52aa8edafb4bfb9ac0e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-23mb/google/brya/var/xol: Limit power limits for low/no battery caseSeunghwan Kim
Xol has a shutdown issue on our reliability test environment: - High temperature - No battery condition It needs to have margin for the PL2 and PL4 values from the adapter power, this will limit the PL2/PL4 values up to 30W/40W for xol's 45W power adapter. The new values are confirmed by our power team. BUG=b:353395811 BRANCH=brya TEST=built and verified MSR PL2/PL4 values. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:18000000 <= MSR PL1 (18W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) [When connected 60W adapter without battery] Before: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:60000000 After: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:30000000 constraint_2_power_limit_uw:40000000 [When connected 45W adapter without battery] Before: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:45000000 constraint_2_power_limit_uw:45000000 After: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:30000000 constraint_2_power_limit_uw:40000000 Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-07-22mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INTSeunghwan Kim
If user continues to use the touchpad for over 3 minutes on Xol, the pointer movement is stuttering. Touchpad I2C transaction should appear during the interrupt signal level is low, but we could see some more I2C transaction after the interrupt signal(GPP_F14) went to high. We found experimentally that changing the interrupt type to GPIO_INT from APIC_IRQ improved this issue. We are still investigating, would like to apply this change first for Xol's dogfooding. BUG=b:350609957 BRANCH=brya TEST=built and verified there's no stuttering issue on touchpad movement Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-07-22mb/google/brya/var/trulo: Configure early and romstage GPIOsSubrata Banik
This change adds early and romstage GPIO configurations for the trulo variant, including: Early GPIOs: - GSC (Google Security Controller) - WP (Write Protect) - UART0 (for serial debug) Romstage GPIOs: - Touch Screen early power sequencing CrOS GPIOs: - CROS_GPIO_VIRTUAL - GPIO_PCH_WP BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ic1b84f61ef62ddbadc2a45758fb3fce90fce0e88 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83568 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/trulo: Add fw_config for PDCSubrata Banik
This patch adds FW Config to the device tree for choosing between the discrete PD chip. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I0a8fb0225edecb063dede31efaec6f2502476977 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add PnP descriptionsSubrata Banik
This patch adds power related entries (FIVR and policy to control lower power c-state transitioning) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ib125c91be79a81f3103dcd587dc685134a292e03 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-07-22mb/google/brya/var/trulo: Add Thermal descriptionsSubrata Banik
This patch adds Thermal related entries (like, TDP, TCC and enabling DPTF config with required sensor configuration) to the devicetree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83565 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-22mb/google/brya: change NAU8825 config to fix headset button detectionTerry Cheong
Brya/brask devices using NAU88L25 are not recognizing headset buttons correctly. The reason is we are using wrong reference voltage of MICBIAS. Use VDDA instead. BUG=b:352215240 TEST=test with 3.5mm headset with buttons on volume up/down and pause Change-Id: I0619021c6fd0a196c318aee58e07dc4149f1d64e Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/variants/orisa: Change board strap memory configRishika Raj
Reorder GPIO pin mapping as per platform documentation: * GPIO_MEM_CONFIG_0 -> GPP_E2 * GPIO_MEM_CONFIG_1 -> GPP_E1 * GPIO_MEM_CONFIG_2 -> GPP_E12 * GPIO_MEM_CONFIG_3 -> NC BUG=None TEST=emerge-nissa coreboot Change-Id: I4e979686833095a904b114500dc1142def583afa Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83549 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-22mb/google/brya/var/trulo: Add Audio descriptionsSubrata Banik
This patch adds descriptions for Audio device (Speaker, Jack and Mic) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ied531dde856fb7c9a410b5667843c9be759cfc8f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add eMMC descriptionsSubrata Banik
This patch adds descriptions for eMMC device (supported mode and DLL tuning) to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I8f1310313b8114731aa417610f245f94c8978ac0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add fw_config probe for storage devicesSubrata Banik
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices, this is used for the first boot in factory. 2. Add fw_config probe to enable/disable devices in devicetree, to avoid suspend(s0ix) fail issue. 3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config is enabled. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ifdaa0bf35413981327097c260ab47e757f697e37 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add CNVi descriptionsSubrata Banik
This patch adds descriptions for CNVi WiFi and BT device to the device tree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I7396917ca7875dcbe1d35a371cc450a9e070b18d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-22mb/google/brya/var/trulo: Add LSIO descriptionsSubrata Banik
This patch adds descriptions for Low Speed I/O (I2Cx, GSPIx, UARTx) to the device tree. It also includes entries that will generate ACPI code at runtime with LSIO end-point device. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I94a3a7f6f85d84407f32ab4c879b236a80859f2d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83550 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/trulo: Add TCSS port descriptionsSubrata Banik
This patch adds descriptions for TCSS port, including over-current (OC) pin configuration, to the device tree. It also includes entries that will generate ACPI code at runtime with port definitions, locations, and type information. Additionally, implement the TCSS PMC MUX programming. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83548 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-22mb/google/brya/var/trulo: Add USB2/3 port descriptionsSubrata Banik
This patch adds descriptions for USB2/3 ports, including over-current (OC) pin configuration, to the device tree. It also includes entries that will generate ACPI code at runtime with port definitions, locations, and type information. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I873810e401c4afdc162036f01bae7247f9b8c749 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-21mb/google/brya/var/trulo: Add minimal devicetree entries to bootSubrata Banik
This patch adds minimal device entries and chip configs for Trulo overridetree.cb to boot. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: Ic8b90dbaaabb439c347a891650d255948d48810a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83546 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya: Centralize EC configuration in trulo baseboardSubrata Banik
This change moves the EC configuration from the orisa variant to the trulo baseboard, enabling reuse by other variants in the future. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: Ib5611cf67a41950c1c4ce936a5d2bea7fdca5c68 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83544 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya: Centralize GPIO configuration in trulo baseboardSubrata Banik
This change moves the GPIO configuration from the orisa variant to the trulo baseboard, enabling reuse by other variants in the future. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83545 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-21mb/google/brya: Enable SKIP_RAM_ID_STRAPS for TRULO variantSubrata Banik
This change enables SKIP_RAM_ID_STRAPS for the TRULO board variant as this board design won't stuff MEM strap GPIO hence, sets the static SPD ID to 0 for the MT62F512M32D2DR-031 DRAM part. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I1acb4680a143611c55f4fa6e032fde38c62af054 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-21mb/google/brya/var/trulo: Populate DRAM configuration parametersSubrata Banik
This patch adds key DRAM configuration parameters as below: - Rcomp - DQ byte map - DQS CPU<>DRAM map - ECT - CCC Mapping - SPD Index Source: Trulo Schematics Rev0.5 (dated June'24) BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: Ie7abc393a71becf26d53ae9e4fc56f66c7117051 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-21mb/google/brya/var/trulo: Add LPDDR5 DRAM (MT62F512M32D2DR-031)Subrata Banik
This patch adds Micron Technology LPDDR5 DRAM (part: MT62F512M32D2DR-031) for Trulo. Make use of spd_tools to generate SPD file after following the below steps: 1. make -C util/spd_tools 2. ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt Output files are: 1. dram_id.generated.txt 2. Makefile.mk BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: Id35f6b57b716375abb66db187413f0f82361d962 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83539 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/nissa/var/glassway: Add WIFI_SAR_ID_1Daniel_Peng
Set "option WIFI_SAR_ID_1 1" for WIFI_SAR_ID field in fw_config. BUG=b:347108861 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I179dad5eeabc1d84aa0a2de5359be5848a2ecc39 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83478 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18mb/google/brya/variants/trulo: Include hda_verb.cSubrata Banik
This change adds hda_verb.c to the ramstage build, but only when the CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB config option is enabled. BUG=b:351976770 TEST=Able to build google/trulo. Change-Id: I9b17126ff1493b5714d6ae715ad2863bdff4ed46 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83499 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-16mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinterEmilie Roberts
Fixes a pmc_mux port mapping error introduced in coreboot commit 4fa8354 Mithrax and felwinter do not have sequential mux_conn[X] to connY mappings which led to the kernel subsystem linking between Type C connectors and USB muxes to be incorrect. The previous patch attempted to fix this by changing the custom_pld layout. However this broke USB usage except for charging. This patch reverts the custom_pld layout and instead changes the pmc hidden and tcss_xhci port mappings to match the hardware layout. BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406 TEST=emerge-${BOARD} coreboot TEST=Manually check that usb-role-switches are mapped to the correct port. Attach USB 3 A to C cable from development machine to left port of DUT. Attach nothing to right-hand port. ectool commands below are only for felwinter as a workaround for devices without a firmware patch to connect superspeed lines. ectool usbpd 0 none ectool usbpd 0 usb ectool usbpd 1 none ectool usbpd 1 usb echo host > /sys/class/typec/port0/usb-role-switch/role (should succeed) ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch) echo host > /sys/class/usb_role/CONX-role-switch/role (should succeed) echo host > /sys/class/typec/port1/usb-role-switch/role (should fail as no cable attached) ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch) echo host > /sys/class/usb_role/CONY-role-switch/role (should fail as no cable attached) BRANCH=firmware-brya-14505.B Change-Id: Iebd259842d3affa259069cd776b46759c1c60712 Signed-off-by: Emilie Roberts <hadrosaur@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83472 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13mb/google/byra: Add VBTs for variants missing themMatt DeVillier
Several brya variants were missing VBT files, add and select them in Kconfig. Also select in Kconfig for VELL, which already had a VBT but was not using/selecting it. TEST=build/boot google/brya (marasov), verify display init functional / payload screen shown. Change-Id: I6848c2b78cf37157299d94bf12c0b6d925ea1432 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83434 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13mb/google/brask/var/bujia: remove DPTF fan controlShon
Fan control is assign to EC handle now. Remove relate setting on coreboot. BUG=b:351917517 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: Iff0776ce3db6f27e250162357abb3c7e9b1a0dc3 Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83380 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-12mb/google/nissa/var/riven: add fw_config probe for storage devicesDavid Wu
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices, this is used for the first boot in factory. 2. Add fw_config probe to enable/disable devices in devicetree instead of variant.c, it can avoid suspend(s0ix) fail issue. BUG=b:328580882 TEST=On riven eMMC and UFS SKUs, boot to OS and run `suspend_stress_test -c 10` pass. Change-Id: I518f1a5955fb88f304663112f1e3d4c744bde183 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83405 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12mb/google/brask/var/bujia: Disable thunderboltShon
Bujia does not support Thunderbolt anymore, therefore disable related TBT setting. The bujia fit image CL, cf. chrome-internal:7468938. BUG=b:349923139 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot. Change-Id: I4301a1f744aa9d4de9f0eba4147c49a4bb3ed922 Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83402 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10mb/google/brask/var/bujia: Add wireless and memory thermal sensorShon Wang
Bujia has 4 thermal sensors, so add two missing sensors settings. BUG=b:351917517 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot. check ACPI SSDT table have new TSR info. $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT check SSDT.dsl Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-08mb/google/trulo/var/orisa: Add fw_config field for PDC controlAmanda Huang
Add a new fw config field to determine which firmware edition shall be flashed to the PDC. BUG=b:334793686 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I817e9415aca1d2f68b484d8e23b581e1a75d6f84 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83353 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Disable CNVi Bluetooth based on fw_configPoornima Tom
When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned off, based on fw_config. Otherwise, when device boots without the cbi settings for wifi6, boot may fail with assertion error for line 817 & 819 of file 'src/soc/intel/alderlake/fsp_params.c'. BUG=b:345596420 BRANCH=NONE TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along with enumeration of corresponding BT device. Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable PCIe Wifi GPIOs based on fw_configPoornima Tom
PCIe based GPIOs of Wifi7 module are enabled based on firmware config. BUG=b:345596420 BRANCH=NONE TEST= Based on fw config configured, wifi6 or wifi7 along with bluetooth ports are detected. Change-Id: If0584e91b5143c6df742961657d242c046409b3a Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable Bluetooth for PCIEPoornima Tom
PCIe based Bluetooth is on port8. This cl enables bluetooth for PCIe based Wifi7 module. BUG=b:345596420 BRANCH=NONE TEST=With proper FW config enabled, BT gets detected on port8 Change-Id: I989cf6122f2555cc89f622e4ce5d21b574d0458e Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83076 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Enable wifi7 on pcie root portPoornima Tom
Enable pcie based, discreete wifi7 on root port4. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi7 module detection based on cbi settings Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Add fw_config fields for wifi6 and wifi7Poornima Tom
Add a new fw config field for wifi category as WIFI_6, which is CNVi based and WIFI_7, which is PCIe based. Also, enable WIFI_6 for existing CNVi based wifi port as well as bluetooth port. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi6 module detection Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83074 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-28mb/google/nissa/var/nivviks: Update config for CNViPoornima Tom
Add wake configuration and set 'add_acpi_dma_property'=true for CNVi. Also, add "set 'add_acpi_dma_property' to true to tell the OS to enforce DMA protection for this device. BUG=b:345596420 BRANCH=NONE TEST=SSDT dump showed below: Scope (\_SB.PCI0.RP01.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x23, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83138 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 12:17:56 +0000