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Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in
brask device tree and add SPD addressese for the two DIMMs.
Separate the Kconfig items of brya and brask. Move
HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya
and add config SPD_CACHE_IN_FMAP to brask.
Add a new section RW_SPD_CACHE to fmd for caching SPD data.
The renamed romstage.c is used by both brya and brask and a new
function variant_get_spd_info is provided to support the different
SPD source types.
BUG=b:194055762
BRANCH=None
TEST=build pass
Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The RW_MRC_CACHE only needs to be 64K for Brya.
BUG=none
TEST="emerge-brya coreboot chromeos-bootimage", flash and boot
brya0 to kernel.
Change-Id: I74365b795e184b92f483ae2bf862791e235c5362
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56989
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel ADL-P supports an additional memory-mapped 16MiB window into the
platform SPI flash. Support for this window already exists at the SoC
level, so all that is needed is to properly organize the flash map to
take advantage of this. FW_SECTION_A moves down to the bottom of the
available space in the lower 16MiB half, and FW_SECTION_B moves to the
bottom of the top 16MiB half. RW_LEGACY is squashed down to 2M.
BUG=b:182088676
TEST=build and boot to OS from FW_MAIN_A
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I60483b7e638c0a7e41f1f7e2b5503ae02e9906bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia1ba8c997680c60ee1eabfae82459e127f664117
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48062
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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