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path: root/src/mainboard/google/brya/acpi
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2023-04-11mb/google/brya/variants/hades: Update GPU power sequencing to add Hades supportTarun Tuli
Add GPU power sequencing changes for the Hades baseboard and variant. Some signals were added, moved or inverted. Based on implementation from Agah. Moved signals: GPIO_1V8_PWR_EN GPP_E11 GPIO_NV33_PWR_EN GPP_E2 GPIO_NV33_PG GPP_E1 New signals: GPIO_NV12_PWR_EN GPP_D0 GPIO_NV12_PG GPP_D1 Inverted signals: GPIO_FBVDD_PWR_EN GPP_A19 ifdef's will be dropped once the Agah variant is retired. BUG=b:269371363 TEST=builds and verified on Agah that DGPU is still detectable (lspci) Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-01mb/google/brya/acpi: Remove extra DC boost byteTarun Tuli
The DC boost bit was intended to be in the Controller Params word rather than its own byte. Correct this error. BUG=b:214581372 TEST=build Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73216 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-15mb/google/brya/acpi: Update checksum in NVPCF DSM subfunctionTarun Tuli
The NVPCF DSM subfunction specified a incorrect checksum. Update this function to the proper checksum of 0xaf. BUG=b:214581372 TEST=build Change-Id: Ib58bd6cc10703ca67a7a4f520273865a95a4702b Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-20mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMSTarun Tuli
1) Update location of TGP (MAGA) to Params2[15:0] 2) Add TPPA (value of 25W) Package: ... Case (0x02) { Local0 = Buffer (0x31) { 0x22, 0x05, 0x10, 0x1C, 0x01 } CreateWordField (Local0, 0x1D, MAGA) CreateWordField (Local0, 0x19, TPPA) CreateDWordField (Local0, 0x15, CEO0) MAGA = 0x50 TPPA = 0xC8 CEO0 = 0x0200 Return (Local0) } ... BUG=b:214581372 TEST=build and verify DSDT on device Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69639 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-11mb/google/brya/var/agah: Correct dGPU Power GPIOsTarun Tuli
PP1800_GPU_X should dynamically move from GPP_E18 to GPP_F12 depending on board revision. PP0950_GPU_X (PEX) should remain on GPP_E10 for all board revisions. BUG=b:242752623 TEST=dGPU is functional on both revisions of the board Change-Id: I20994fcac4d7b98ee893d5eb98b096c037d31d6c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70320 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-26mb/google/brya/var/agah: Update PEXVDD enable GPIO for next board revTim Wawrzynczak
The next rev of this board will move the dGPU PEXVDD enable pin from GPP_E10 to GPP_F12. This patch handles both the old and newer revisions by using an ACPI Name to hold the GPIO # for PEXVDD enable. It also cleans up the GPIO handling a little bit between board revs. BUG=b:242752623 TEST=dGPU is functional and power sequencing tests still pass on board rev 2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icc7968777f86ab07561b0a861b7d22ec714d1c34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-22mb/google/brya/acpi: Don't clear GC6 flag after GC6 entryTim Wawrzynczak
According to Nvidia, the GC6 flag (DFEN) should not get cleared after a successful GC6 entry; the kernel driver will not re-inform ACPI that the exit should be GC6 exit as well. BUG=b:243888246 BRANCH=brya TEST=tested by Nvidia Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I220795928d03f269de48278ea0ab57de7253fad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67745 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12mb/google/brya/acpi: Move dGPU power checks earlierTim Wawrzynczak
Linux always "turns on" a PowerResource when it boots, regardless of _STA, so the _ON routine should be idempotent. In this case, it all is, except for the LTR restore, which would restore a value of 0 when _ON is run the first time, which means that LTR is disabled on the root port from then on, as the save/restore routines will keep saving/restoring that 0. THis patch fixes the problem by moving the power checks from PGON/PGOF to GCOO/GCOI. BUG=b:244409563 TEST=boot agah and verify that LTR is still enabled on the root port Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4ed78323608eede5b8310598f1f1115497ab2b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67278 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12mb/google/brya/acpi: Remove erroneous _PR0/_PR3Tim Wawrzynczak
The Linux kernel runtime D3 framework expects a PCIe device to have a power resource in order to be properly power-manageable. The _PR0/_PR3 values were pointing at the PEG0 Device, which is not a PowerResource, so this must have confused the RTD3 framework and RTD3 was not functional. Removing the _PR0/_PR3 fixes the problem. BUG=b:243888246 TEST=echo auto > /sys/bus/pci/devices/0000:01:00.0/power/control; sleep 10; echo on > /sys/bus/pci/devices/0000:01:00.0/power/control After this there are no longer errors seen in dmesg about failing to place the device into D0. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/67212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-12mb/google/brya/acpi/power: Clean up ASL codeTim Wawrzynczak
Mostly there are too many extraneous `\_SB.PCI0.` prefixes, also a few minor cleanups, but nothing functional. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I79d919d2f04f57232f8f6a4e4d0690833faeb834 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12mb/google/brya/acpi: Save/restore/clear some registers over GCOFFTim Wawrzynczak
Similar to the prior CL (commit db8ad5e), do the same register dance before/after GCOFF. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8fecba40c5a5af11e24f82db07face3ce10481bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67086 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-01mb/google/brya/acpi: Save/restore/clear some registers over GC6Tim Wawrzynczak
Nvidia recommends saving and restoring the LTR Enable bit in PCIe config space for the PCIe root port before/after GC6 entry. Also the detectable error bit should be cleared, as there may be errors expected during the GC6 flow. BUG=b:214581763 TEST=no more correctable errors after GC6 entry/exit Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I058ce1b3f17fb6cc59785a85efaf9ea0504cf2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/66808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-18mb/google/brya/acpi: Add PCIe SRCCLK# control to RTD3 methodsTim Wawrzynczak
This patch adds support for turning the PCIe SRCCLK# on and off during RTD3 (just like the soc/intel/common/block/pcie/rtd3 driver). TEST=GC6 and GCOFF sequences still work Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4b369cfcc7245a1c212fa65f65fdab542f60e196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-18mb/google/brya/var/agah: Update NVVDD VR PGOOD GPIOTim Wawrzynczak
For board revs 3 and later, the PG pin for the NVVDD VR moved from GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that this code will write the correct GPIO # to depending on the board rev, and we'll use that instead. BUG=b:239721380 TEST=still works on board rev 2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-16mb/google/brya/acpi: Add minimum off timer for GCOFFTim Wawrzynczak
By moving the large wait for FBVDD discharge from PGOF to PGON, the whole time may be avoided if enough time has elapsed between the successive calls. BUG=b:239719056 TEST=With Nvidia test software, verify ACPI prints Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I891aa14f120d58c45b8965038a9d2f2a417b3f3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-16mb/google/brya/acpi: Fix GC6 entry and exit sequencesTim Wawrzynczak
Now that the virtual wire situation is figured out, the GC6 sequence is updated to match the latest HW design guide from Nvidia. This allows Nvidia test software to (mostly) successfully execute the GC6 test, but with some PCIe AER errors. BUG=b:214581763 TEST=tested with Nvidia test software Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia094c4fa9b4db094a59b9b6f02be1a649ee8569b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-07mb/google/brya/acpi: Fix PERST# handling in GC6 exitTim Wawrzynczak
PERST# is supposed to be de-asserted in GC6 exit, but the original patch used the CTXS Method, which drives a GPIO low, instead of STXS, because PERST# is active-low. This patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib0adb8efe5e2cc733ae2228614c58c124ba3f11b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-07mb/google/brya/acpi: Fix NVJT subfunction IDsTim Wawrzynczak
The POWERCONTROL and PLATPOLICY NVJT subfunctions were incorrectly set to 2 and 3, respectively. While looking at the ACPI code, Nvidia noticed these are supposed to be 3 and 4, also respectively, so this patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0f808aba7072b943ee2fad20e06ff39a9b54903d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-07-28mb/google/brya/acpi: Add L23 entry/exit sequences during dGPU GCOFFTim Wawrzynczak
When the dGPU is entering GCOFF, the link should first be placed into L2/L3 as appropriate for the design, then when exiting, the link should be placed back into L0. This patch fixes that oversight. BUG=b:239719056 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-28mb/google/brya/var/agah: Optimize dGPU GCOFF entryTim Wawrzynczak
After staring at lots of scope shots, the EE has determined that a few modifications to the GCOFF sequence can be made: - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion - Remove delay after ramping down FBVDD This patch implements these minor changes. BUG=b:240199017 TEST=verified by EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-22mb/google/brya/acpi: Poll more frequently in GPPLTim Wawrzynczak
The full dGPU power-on sequence, when executed from ACPI, is taking roughly 15ms or so, which puts it close to the maximum of 20ms required from the Nvidia spec. Changing the polling period to 100 us instead of 1 ms drastically reduces the time required for this sequence, now taking typically 7 ms or so. This gives a lot more margin during the power on sequence. BUG=b:238466724 TEST=Sequence verified by EE on a scope Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3ba676c5fac983a0c1ad1d60c3863d06ed33fa27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66020 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-20mb/google/brya/acpi: Add support for D Notify event from the Chrome ECTim Wawrzynczak
The agah EC code includes a driver to keep track of the current D Notify level that the GPU should be at. When it changes, it will send a host event to the ACPI FW, which will then pass that Notify on to the kernel driver. This patch adds support for that feature, which is described in the Nvidia Software Design Guide. BUG=b:229405562 TEST=add Printf() calls to the ACPI, and work through the various scenarios on the EC that will cause D Notify levels to change; this will cause the Printfs() to show up in the kernel log. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5cd8bd7d177ea10a165613ed0726a6d6fd86c226 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13mb/google/brya/acpi: Fix GPIO assignment for GPIO_GPU_NVVDD_ENTim Wawrzynczak
GPIO_GPU_NVVDD_EN is incorrectly (duplicately) assigned to GPP_A19 in power.asl, but a double check of the schematic shows that the actual pad is GPP_A17, so this patch fixes that. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4432b50c737508b7e0d595423d614a723d2499c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13mb/google/brya/acpi: Remove NV_33 power rail from GC6 entry/exit sequencesTim Wawrzynczak
I misread my notes when writing the code for the GC6I/GC6O Methods, and accidentally included NV_33 in the GC6 sequence, which is incorrect (confirmed in the Hardware Design Guide). This patch removes the code that brings NV_33 up and down during the GC6 sequences. BUG=b:236676400 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iaa6c5ef3d7b1edbe13257f99013ab0e4382bdbf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65565 Reviewed-by: Robert Zieba <robertzieba@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13mb/google/brya/acpi/peg: Fix Power Resource _ON and _OFFTim Wawrzynczak
The _ON and _OFF methods for the root port's power resource were calling the _ON and _OFF in the PEGP namespace, which was the incorrect method, it should have been NPON/NPOF, so this patch updates that. BUG=b:236676400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3653996329473f133e3f0d53306882dc3213b6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13mb/google/brya/acpi: Update GPIO polling methodTim Wawrzynczak
The preferred way of polling in ACPI I've seen is usually to just divide the sleep into N chunks, and ignore the time taken in between. This works in practice (validated with Timer calls before and after). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4a2cd82cea05c539eff30b9b9d6ef18550d17686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13mb/google/brya/acpi: Modify NBCI _DSM subfunctionTim Wawrzynczak
The NBCI "get callbacks" _DSM subfunction should utilize the same "get callbacks" subfunction from the GPS _DSM subfunction; this patch adds that Method call into the ACPI code. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idf2f148b5a95acccb02f47cba1ef33a9fc16bcd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13mb/google/brya/acpi: Keep track of dGPU power stateTim Wawrzynczak
To avoid extraneous calls from the kernel to _ON or _OFF, keep track of the power state of the GPU in an integer and exit _ON and _OFF routines early when attempting to enter the current state. BUG=b:236676400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie874fcdc7022c4fde6f557d1ee06e8392ae3d850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-07mb/google/brya/var/agah: Update FBVDD power-down delayTim Wawrzynczak
The EEs have observed the ramp down delay on this signal in more detail and 40 ms can still meet the sequencing requirements. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-24mb/google/brya/{var/agah,acpi}: Update GPU GCOFF sequence for power downTim Wawrzynczak
We have clarified the powerdown sequence with Nvidia, and the EEs have come up with this modified sequence which still meets the requirements from the hardware design guide. BUG=b:233959099 TEST=Verified by ODM and EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I37715165ab488f994c825fb9ff532ebf8d7f4cb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-08mb/google/brya: Add GPS _DSM subfunction support for Nvidia GPUTim Wawrzynczak
The _DSM subfunction for the Nvidia GN20 supports 1 additional subfunction, known as GPS, which is required to support GPU Boost. This implementation is minimal, essentially letting the GPU manage its own temperature. BUG=b:214581372 TEST=abuild Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I21331bd811a13212f3825bda44be44d1b5ae7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08mb/google/brya/var/agah: Fix ACPI power sequencingTim Wawrzynczak
Now that the power sequencing for the GPU is in a better shape, ensure that the ACPI code that performs power sequencing matches the C code that does the same. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-06mb/google/brya/acpi: Add support for NVPCF _DSM subfunctionTim Wawrzynczak
The Nvidia GPU kernel driver supports another _DSM subfunction which is known as NVPCF (Nvidia Platform and Control Framework). The subfunction informs the kernel driver about Dynamic Boost parameters, which is done at init time, but can also be changed dynamically. BUG=b:214581372 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7887bfc2e8e1cae606e12502a9eda3a7954c8d7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20mb/google/brya/acpi: Add support for NBCI _DSM subfunctionTim Wawrzynczak
The Nvidia GPU supports another function named NBCI (NoteBook Common Interface), which has some subfunctions which are required for the Nvidia kernel driver to consume. The specification for this function comes from the Nvidia GN20 Software Design Guide. BUG=b:214581763 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20mb/google/brya: Add PEG and initial Nvidia dGPU ASL supportTim Wawrzynczak
Some brya variants will use a GN20 series Nvidia GPU, which requires quite a bit of ACPI support code to be written for it. This patch lands a decent bit of the initial code for it on the brya platform, including: 1) PEG RTD3 methods 2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods) 3) NVOP _DSM method There will be more support to come later, this is all written to specifications from the Nvidia Software Design Guide for GN20. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 16:15:47 +0000