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path: root/src/mainboard/google/brya/Makefile.inc
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2023-01-12mb/google/brya: Add romstage early graphics for bryaJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b514 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71696
2023-01-04Revert "mb/google/brya: Add romstage early graphics for brya"Jakub Czapiga
This reverts commit 96d9b756690839c17b307a93b8a1898bd1c02ff5. Reason for revert: Merged out of order, broke tree Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya: Add romstage early graphics for bryaJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2021-10-04mb/google/brya: Enable DDR4 SODIMM for braskDavid Wu
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in brask device tree and add SPD addressese for the two DIMMs. Separate the Kconfig items of brya and brask. Move HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya and add config SPD_CACHE_IN_FMAP to brask. Add a new section RW_SPD_CACHE to fmd for caching SPD data. The renamed romstage.c is used by both brya and brask and a new function variant_get_spd_info is provided to support the different SPD source types. BUG=b:194055762 BRANCH=None TEST=build pass Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-03mb/google/brya: Introduce new baseboard braskZhuohao Lee
This patch initiates the brask setting which includes the gpio and device tree setting. BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: I1bb42c7bb2492402de0810bc4ab2e8d8c0e2392b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-29mb/google/brya: add BASEBOARD_DIR to support different baseboardZhuohao Lee
In order to support different baseboard configuration, we add the BASEBOARD_DIR to switch the directory. The expected structure looks like: mb ..|_ google .........|_ brya .............. |_ variants .....................|_ baseboard ..............................|_ brya ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ..............................|_ brask ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ......................|_ brya_variant1 ......................|_ brya_variant2 ......................|_ ... ......................|_ brask_variant1 ......................|_ brask_variant2 ......................|_ ... ...............|_ <all mb common code> BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ic99e42dbbd27fa3e1f6cb3a1b5daee1c8c7b1083 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-27mb/google/brya/var/brya0: Use auto-generated Makefile.incAmanda Huang
This change adds mem_list_variant.txt that contains the only memory parts used by brya0 for Proto-0 build and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. BUG=b:176491791 Change-Id: I3fe755564e7541a7abdfca0e5aa7fd786f5ca880 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-24arch/x86: Use wildcard for mb/smihandler.cKyösti Mälkki
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Add EC smihandlerEric Lai
Add implementation of EC smihandler BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48115 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/brya: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock and ramstage. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia658ab4b466242cf8658abb239f19a9c0a03849a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/brya: Add entry stubs of each stageEric Lai
Add entry point stubs of each stage for Brya. More functionalities will be added later. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I44934c05ee32090b6e34648ee02f004c83e93d57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48063 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 04:24:07 +0000