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path: root/src/mainboard/google/brya/Kconfig
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2023-06-27mb/google/hades: select DUMP_SMBIOS_TYPE17Eric Lai
Hades uses DDR5 which can't read SPD from coreboot yet. Use smbios dump to print memory information. TEST=check the coreboot log. memory Channel-0-DIMM-0 type is DDR5 memory part number is MTC8C1084S1SC56BG1 memory max speed is 5600 MT/s memory speed is 5200 MT/s memory size is 16384 MiB Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ica44081228a3a1edc36e2110e84686582fbe8f33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-06-15{driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version configSubrata Banik
This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config is clear. Any platform would like to fetch the currently running ISH firmware version should select this configuration. TEST=Able to build and boot google/marasov. Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-08mb/google/brya: Enable GPU ACPI for HadesTarun Tuli
Include the GPU ACPI methods for all of Hades baseboard. BUG=b:285981616 TEST=built for Hades and verify shutdown works Change-Id: Iec3c4b59a9e7a9d4a902db51d40b60e114521774 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-07mb/google/nissa/var/joxer: Remove VBOOT_GSC_BOARD_ID configReka Norman
Board IDs are now filled in as part of the signing process, so we don't need to set them in coreboot. BUG=b:240620735 TEST=Build and check VBOOT_GSC_BOARD_ID is set to ZZCR. Change-Id: I7dda8ad59046a1dd9a28595e037eda86e91c98df Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75641 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14mb/google/hades: Correct TPM I2C bus to 3Eric Lai
Follow schematic to correct I2C bus. BUG=b:282164589 TEST=able to boot up Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I277e5190302c98dbce809d09c1a32fac758aa8e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-11mb/google/brya: Create gothrax variantYunlong Jia
Create the gothrax variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=279614675 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GOTHRAX Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I129e4a55e4b87091e425a45392024d04f3977c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-04mb/google/brya: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on banshee and osiris variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I12614b85f9779cc40d83a9c868cc46b110f26af6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74817 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-22mb/google/brya: Enable CSE FPT Info config for NissaSubrata Banik
Google Brya variants like Nissa family selects `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` to store CSE FPT information. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74387 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-17mb/google/brya/variants/hades: Update GPIO configsTarun Tuli
Update GPIO configs based on latest schematics (revision aabe36) Move GPP_D4->GPP_A13 (BT_DISABLE_L) Swap GPP_E3<>GPP_E8 (WIFI_DISABLE_L and PG_PPVAR_GPU_NVVDD_X_OD) Move GPP_A13->GPP_A20 (GSC_PCH_INT_ODL) BUG=b:269371363 TEST=builds Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-14mb/google/hades: move PCIEXP_SUPPORT_RESIZABLE_BARS to commonEric Lai
All the variant will use the same dGPU, so make PCIEXP_SUPPORT_RESIZABLE_BARS common. BUG=b:277974986 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: If8618f2da3133c6b52427375c55a69d7014c4881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74371 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-07mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-05Revert "mb/google/brya: Enable asynchronous End-Of-Post"Nick Vaccaro
This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32. Revert initial change as it was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04soc/intel/alderlake: Add support for CSE timestamp data versionsBora Guvendik
CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1. BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps. Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-03mb/google/nissa/var/uldren: Add overridetreeVan Chen
Add override devicetree based on schematics(ver. 20230308). BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9cd918c6a48cc6007a18c5aa94afe31fd9608718 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73974 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-31mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-30mb/google/nissa/var/yavilla: Update devicetree settingTony Huang
Update devicetree according to yavilla's design. Add Kconfig for TPM I2C bus. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I1b44436a7f93d62764d0451c738ae33976a24a15 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-03-17mb/google/brya: Create yavilla variantTony Huang
Create the yavilla variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVILLA Change-Id: I4539090da5e1db474a8f58a42aecc38659959f75 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-14mb/google/brya: Create uldren variantvan_chen
Create the uldren variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:271513530 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ULDREN Change-Id: Ibbcd34fb4ef1f7464f0c94d2fcf75280c3eed6be Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73680 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-07mb/google/hades: Change memory to SODIMMEric Lai
Add SODIMM support, drop the solderdown based on schematics. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I85ec79c3d8f1147a875c4d04017bb50347121ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-04mb/google/brya: remove the skolas baseboardNick Vaccaro
The skolas baseboard is no longer needed, so this change removes the baseboard files for skolas and adjusts the config settings to that variants that used to select BOARD_GOOGLE_BASEBOARD_SKOLAS now select BOARD_GOOGLE_BASEBOARD_BRYA and SOC_INTEL_RAPTORLAKE. BUG=b:271470530 TEST="emerge-brya coreboot chromeos-bootimage", flash image-skolas.bin onto a skolas and verify it boots to kernel. Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-16mb/google/brya: Add new baseboard hades with variants hadesEric Lai
Add a new baseboard for hades, an Intel RPL based reference design. Also, add variants for the reference boards hades. This commit is a stub which only adds the minimum code needed for a successful build. Need update gpio and memory DQ pins after final shchematic comes out. BUG=b:269371363 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-02-15mb/google/brya: Add Kconfig for TPM I2C busZoey Wu
Add TPM I2C for aurash to avoid TPM I2C fail. BUG=b:269050049 TEST=emerge-brask coreboot. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: I1947d2e1189f46d8dab01837f75de7cb6e9e0579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10mb/google/brya/var/constitution: Add SOLDERDOWN supportMorris Hsu
Constitution will use SOLDERDOWN. Add memory.c to override baseboard. Add mem_parts_used.txt and generate dram_id.generated.txt and Makefile.inc Memory: SAMSUNG K4U6E3S4AB-MGCL MICRON MT53E1G32D2NP-046 WT:B BUG=b:267539938 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72775 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09mb/google/brya: Create aurash variantZoey Wu
Create the aurash variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:263691099 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_AURASH Change-Id: I595102778071f822c5cf69ceadeed174e5ea4836 Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72837 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07mb/google/brya: Create constitution variantMorris Hsu
Create the constitution variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:267539938 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CONSTITUTION Change-Id: Idb6089561d3aa5aac4448f9d46347c731f027e9c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72730 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22Revert "mb/google/brya: Add EC mux device to brya0"Anil Kumar
This reverts commit 197d550d069f918698fa7cd8dda73e09fbfda30c. Reason for revert: breaks TBT and TypeC display on Brya0 Bug=265375098 Branch=firmware-brya-14505.B Test=Build and boot Skolas board with Brya0 image. Test TBT and TypeC display functionality. Change-Id: Ia0283b023949476e90edff7151d605fa36331bfd Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72081 Reviewed-by: Prashant Malani <pmalani@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-10chromeos/cr50_enable_update.c: Clear EC AP_IDLE flagDerek Huang
When AP boots up after Cr50 firmware update and reboot, AP finds that Cr50 reset is required for Cr50 to pick the new firmware so it trigger Cr50 reset and power off the system, AP expects system will power on automatically after Cr50 reset. However this is not the case for Chromebox, Chromebox EC set AP_IDLE flag when system is shutting down, when AP_IDLE flag is set in EC, the system stays at S5/G3 and wait for power button presssend. It cause an issue in factory that the operator needs to press power button to power on the DUT after Cr50 firmware update. This patch sends EC command to direct EC to clear AP_IDLE flag after AP shutdown so AP can boot up when Cr50 reset. BUG=b:261119366 BRANCH=firmware-brya-14505.B TEST=DUT boots up after Cr50 firmware update in factory test flow Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/google/brya: Allow respective variant to choose NEM configSubrata Banik
This patch introduces a new config named `DEFAULT_ADL_NEM` and allows respective brya variants with Alder Lake ESx samples to choose NEM over eNEM as eNEM was fuse disabled till ESx. TEST=The boot flow related to eNEM and NEM behaviour remains the same with and without this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/71743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09mb/google/brya: Increase Resizable BAR address space limit to 33 bitsTarun Tuli
The dGPU used for some Brya projects requests 33 bits of address space for one of its BARs via the Resizable BAR mechanism (requires 6GB). This Kconfig is currently set at 32 bits for brya, so the allocation currently is capped at 32 bits (4GB). This patch sets the limit to 33 bits for brya boards, which is enough for the GPU. BUG=b:214443809 TEST=all of the dGPU PCI BARs on agah can be successfully allocated Change-Id: Ia791be5108fb07a256ae62fc2aee2f057909ef12 Signed-off-by: Tarun Tuli <tarun@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08mb/google/nissa: Enable eNEMReka Norman
Enable eNEM for all nissa variants. This is mostly done to be consistent with other recent Intel platforms. It's not strictly necessary since on nissa the LLC size is larger than the total code + data size used in CAR. There is no change in boot time. BUG=None TEST=Boot to OS on craask Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-06mb/google/brya/var/omnigul: use i2c1 for TPMjamie_chen
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the omnigul variant. BUG=b:263060849 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804 Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-06mb/google/nissa: Disable stage cacheReka Norman
Although S3 is supported on nissa, only S0ix is used on user devices, so we can ignore optimising the S3 resume time. Disable the stage cache to save boot time at the cost on increasing the S3 resume time. Boot time is reduced by ~6 ms. This is mostly from adding postcar to the stage cache, which is slow since TSEG is not cached in romstage. Adding ramstage and FSP-S take negligible time. The S3 resume time is increased by ~89 ms total from loading and decompressing ramstage and FSP-S. Boot time before: 3:after RAM initialization 573,295 (931) 4:end of romstage 583,569 (10,274) 100:start of postcar 587,729 (4,160) Boot time after: 3:after RAM initialization 571,527 (830) 4:end of romstage 575,712 (4,185) 100:start of postcar 579,866 (4,153) S3 resume time before: 101:end of postcar 368,904 (0) 10:start of ramstage 369,165 (260) 971:loading FSP-S 385,742 (16,577) 30:device enumeration 407,105 (21,362) S3 resume time after: 101:end of postcar 363,101 (0) 8:starting to load ramstage 363,101 (0) 15:starting LZMA decompress (ignore for x86) 382,802 (19,701) 16:finished LZMA decompress (ignore for x86) 431,620 (48,817) 9:finished loading ramstage 431,850 (230) 10:start of ramstage 431,927 (76) 971:loading FSP-S 448,357 (16,430) 17:starting LZ4 decompress (ignore for x86) 474,420 (26,062) 18:finished LZ4 decompress (ignore for x86) 474,627 (206) BUG=b:247940538, b:192032803 TEST=Boot and S3 suspend/resume on craask Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71677 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-05mb/google/brya: Create omnigul variantjamie_chen
Create the omnigul variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:263060849 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OMNIGUL Change-Id: I6b4123db9cb77dc050a81f1cb83ef10e2fbffe8d Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-04Revert "mb/google/brya: Define a more suitable MRC training text message"Jakub Czapiga
This reverts commit e45f70423e5da8509bae83aba84b08f8fc0f624e. Reason for revert: Merged out of order, broke tree Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I38a7be6b94199d3a23e78114fb6708c535f241cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-04mb/google/brya: Define a more suitable MRC training text messageJeremy Compostella
This message is designed to reduce end-user confusion who may not know what memory training is. It also provides a maximum time estimation calibrated for brya devices. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=New message observed on skolas Change-Id: Ie71cd86746427789b3694d41224bf2c170af0f91 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70796 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04mb/google/brya/var/gaelin: Use RPL FSP headersMike Shih
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP. Since we use RPL FSP and it will support ADL as well, we rename "Gaelin4ADL" to "Gaelin". BUG=b:258603624 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Cq-Depend: chrome-internal:5227091, chromium:4113361 Change-Id: Ie7349f3670aeec166228e7df55300cd30d0ca16c Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-30mb/google/brya: Enable crashlogGaggery Tsai
This patch enables crashlog for all brya projects. BUG=b:190756531, b:259978562 BRANCH=None TEST=emerge-brya coreboot chromeos-bootimage & ensure the crashlog PCIe device 0xa.0 is enabled and intel-pmt kernel driver is loaded. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Ib632c8ac9ea7a4f0e0b08b96eb149f8ef1386be0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68526 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-16mb/google/brya/var/gaelin: Configure DRIVER_TPM_I2C_BUSRaymond Chung
Add TPM I2C bus for gaelin in Kconfig. BUG=b:249000573 BRANCH=firmware-brya-14505.B TEST=Build "emerge-brask coreboot" and can boot to OS. Change-Id: Idaac11111a9ba7df0929267567e4730b2811f5f0 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68886 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2022-11-15mb/google/brya/var/marasov: use i2c1 for TPM for marasovFrank Chu
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the marasov variant. BUG=b:254365935 TEST=FW_NAME=marasov emerge-brya coreboot Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I4d155fb35424d1ec12e825ca0aab233bd3cd607e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69376 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-11mb/google/brya/var/gladios: use i2c1 for TPM supportKevin Chiu
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the gladios variant. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69424 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-07mb/google: Probe p-sensor only for selected variantsVictor Ding
Only a subset of variants has proximity sensors. This patch by itself does not introduce functional changes to any board. It is mainly to ease migrating SX9324 from the legacy driver to the linux one - allowing gradual migration variant by variant. BUG=b:242662878 TEST=Dump ACPI SSDT then verify they are identical w/ and w/o this patch Change-Id: Ic00e0d9eafcef2c9eaf32571fecf6190777cec36 Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69191 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07mb/google/brya: Create marasov variantFrank Chu
Create the marasov variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:254365935 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MARASOV Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ibe2dc442480f6a73877b40625e228cdb2038aa4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69052 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-27mb/google/brya/var/lisbon: use i2c1 for TPM for lisbonKevin Chiu
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the lisbon variant. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I16be50258db2111d22f7465458873e92f44c7dac Reviewed-on: https://review.coreboot.org/c/coreboot/+/68887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRYReka Norman
On nissa, the pre-x86 time is not part of the 1s firmware boot time target. Including the pre-x86 timestamps causes confusion since the boot time appears to be greater than 1s, so disable the Kconfig on nissa. We're not doing any analysis or optimisation of the pre-x86 time on nissa anyway, this work will start from MTL onwards. Also, the Kconfig is already disabled on the brya firmware branch, so this will result in the same behaviour as brya. Before: Total Time: 1,205,840 After: Total Time: 995,300 BUG=b:239769532 TEST=Boot nivviks, check "1st timestamp" is the first timestamp. Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20mb/google/brya: Create gladios ADL variantKevin Chiu
Create the gladios variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:239513596 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_gladios Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I3dc99d97d8e30d9641f56616222dd68e3a0d548d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17mb/google/brya: Guard FMD selection with CHROMEOSMatt DeVillier
Allows brya boards to use coreboot-generated FMAP layout when building for non-ChromeOS target. TEST=build/boot brya/banshee with edk2 payload, non-ChromeOS build Change-Id: I21c2247c034d9bdc49f66771a93abad542a1e1fa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-11mb/google/brya/nivviks: Enable ISH driver and firmware nameMeera Ravindranath
BRANCH=none BUG=b:234776154 TEST=build and boot Nirwen UFS, copy ISH firmware to host file system /lib/firmware/intel/adln_ish.bin check "dmesg |grep ish", it should show: ish-loader: ISH firmware intel/adlnrvp_ish.bin loaded Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I89782b0b7dde1fca0130472a38628e72dfd5c26c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-10brya: add new zydron variantDavid Wu
Add a new zydron variant, which is a variant of brya's skolas baseboard. currently copy the variant file from kano. BUG=b:250787251 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49a41678568daef80b7cd1e3ed60ce4763034f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68130 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-04soc/intel/alderlake: Fix UFS OCP fabric timeoutMeera Ravindranath
The delayed return of certain fetch instruction from memory to the UFS causes the OCP fabric to timeout on the transaction and become non-responsive. As recommended by the SoC and IP teams,program the OCP fabric register to avoid the timeout in the OCP fabric. This patch adds the following changes 1. Program the OCP fabric registers in the PS0 routine. 2. Move the ssdt contents of UFS to dsdt asl code to avoid duplication of UFS device creation BUG=b:240222922 TEST=Build and boot Nirwen UFS board, observe no system hang during Chrome PLT test. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-02mb/google/brya: Create lisbon variantKevin Chiu
Create the lisbon variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:246657849 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_LISBON Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ia31752765657054b28ea16b046b63c38a72f95bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-09-19mb/google/brya/var/brya4es: deprecate brya4esNick Vaccaro
The brya4es variant is no longer needed, removing code for brya4es. BUG=b:246611270 TEST=None Change-Id: I9b222f89fe766c63158518713be19d7959451721 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-04mb/google/brya/var/ghost: Delete variantJack Rosenthal
This project concluded and the coreboot implementation is no longer required. BUG=b:244596639 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67299 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29drivers/i2c/tpm: Remove TI50_FIRMWARE_VERSION_NOT_SUPPORTEDReka Norman
This workaround was added since reading the firmware version on Ti50 versions < 0.0.15 will cause the Ti50 to become unresponsive. No one is using Ti50 this old anymore, so remove the workaround. BUG=b:224650720,b:236911319 TEST=Boot to OS on nivviks with Ti50 0.22.4. Check the log contains the firmware version: [INFO ] Firmware version: Ti50/D3C1 RO_B:0.0.26/- RW_B:0.22.4/ti50_common:v095c Change-Id: I3628b799e436a80d0512dabd356c4b2566ed600a Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-22brya: add new skolas variantNick Vaccaro
Add a new skolas variant, which is a variant of brya's skolas baseboard. BUG=b:242869976 BRANCH=firmware-brya-14505.B TEST=none Change-Id: I7f9f0389d8b1bf75d8652cbcc9d0c15d3a529802 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17mb/google/nissa: Create yaviks variantWisley Chen
Create the yaviks variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:242277219 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVIKS Change-Id: Id60fe0e54a8e0196a302141f58c6695779ac251a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-17mb/google/brya/var/ghost: Enable NXP UWB SR150 chipJack Rosenthal
Add GPIO configuration and device tree to enable the chip. BUG=b:240607130 BRANCH=firmware-brya-14505.B TEST=Patch linux with NXP's pending drivers UWB device is probed and can respond to a simple hello packet Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17mb/google/brya/var/ghost: Add max98396 supportEric Lai
Ghost has two amps and address are 0x3c and 0x3d. BUG=b:231581723 BRANCH=firmware-brya-14505.B TEST=max98396 driver can get the DSD property correctly. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3b6a331ca42e97f984f3a585726c02452bb067f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-14mb/google/brya/var/ghost: Enable cameraJack Rosenthal
Add OV 5675 MIPI camera to ghost, sensor eeprom, and IPU device to device tree. Enable config for MIPI camera. BUG=b:241343306 BRANCH=firmware-brya-14505.B TEST=with ghost overlay changes, camera in camera app works Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ie079e43ae0f34efba396331922ea4a89eda72128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-08mb/google/brya: Select SOC_INTEL_COMMON_UFS_SUPPORT for NissaMeera Ravindranath
BUG=b:238262674 TEST=Build and check ufs.c file gets compiled for Nissa boards Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: Idc5ad922b97bd1e65e5023f9126c43e42cfc38a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66064 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07mb/google/brya/var/ghost: Disable LID_SHUTDOWNCaveh Jalali
The lid sensor is on a daughterboard which can cause unintended shutdowns when not connected. Disable lid sensor based shutdown behavior in depthcharge until we have a better solution. BUG=b:240005819 BRANCH=firmware-brya-14505.B TEST=booted ghost, no longer shuts down due to missing lid sensor Change-Id: I69f70255dee1b69e05b112c0174f5f52d1368837 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-29mb/google/brya/var/ghost: Enable CS42L42 codecEric Lai
Add CS42L42 support in device tree. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check cs42l42 driver can probe successfully in kernel. cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-29mb/google/brya: Create gaelin variantRaymond Chung
Create the gaelin variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:239514438 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GAELIN Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-07-22mb/google/brya/var/ghost: Split ghost4adl into 3 variantsJack Rosenthal
We plan to make 3 firmwares which differ only by Kconfig options and can share a common variant directory. ghost4adl: Board with an ADL chip. ghost4es: Board near identical but has RPL-ES chip. ghost: Will have final RPL silicon. Since they will only differ by Kconfig options and Intel binary blobs, let's not duplicate the variant directory but instead share it in common. BUG=b:239456576 BRANCH=firmware-brya-14505.B TEST="make menuconfig", verify layout of board selection Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-21mb/google/brya/var/baseboard/skolas: set BOARD_ROMSIZE_KB_32768Nick Vaccaro
Skolas baseboard needs to set BOARD_ROMSIZE_KB_32768, so this change sets it. BUG=b:239628052 BRANCH=firmware-brya-14505.B TEST="emerge-brya coreboot" and verify that the following configs are set as: CONFIG_BOARD_ROMSIZE_KB_32768=y CONFIG_COREBOOT_ROMSIZE_KB_32768=y CONFIG_COREBOOT_ROMSIZE_KB=32768 CONFIG_ROM_SIZE=0x02000000 Change-Id: I0846b8e69c8b65e010eef9a8f4a88606197cd0c6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-06mb/google/nissa: Select Kconfig to perform CSE FW update in ramstageKrishna Prasad Bhat
Alder Lake-N based nissa boards use compressed ME_RW blobs for CSE FW Update. Choose SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE Kconfig to perform CSE FW sync in ramstage. BRANCH=firmware-brya-14505.B TEST=Perform CSE FW upgrade/downgrade on nivviks. Change-Id: I00630096c52434f44914f3ae82ff043ecf77b80d Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65368 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-30mb/google/nissa: Add fmd for debug FSPKangheui Won
Debug FSP is ~850KiB larger than release FSP and we don't have sufficient space for nissa flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. Note: This fmd will only used for internal testing/debugging and not for the firmware in released devices. BUG=b:231395098 TEST=build with CONFIG_BUILDING_WITH_DEBUG_FSP Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Idb17f003285575e80feb86bb292b95daf0f5b3b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-28mb/google/brya/var/skolas4es: use i2c1 for TPM for skolas4esNick Vaccaro
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the skolas4es variant. BUG=b:230773725 TEST=None Change-Id: I12b05cdacdd26bfffff47b7a3fb127aa7778f15d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65493 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23mb/google/brya: Create xivu variantIan Feng
Create the xivu variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:235025984 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_XIVU Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I12341a2414e58ebc1c22429d35a03afef27adace Reviewed-on: https://review.coreboot.org/c/coreboot/+/65235 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-21security/vboot: Add support for GSCVD (Google "RO verification")Julius Werner
This patch adds a new CONFIG_VBOOT_GSCVD option that will be enabled by default for TPM_GOOGLE_TI50 devices. It makes the build system run the `futility gscvd` command to create a GSCVD (GSC verification data) which signs the CBFS trust anchor (bootblock and GBB). In order for this to work, boards will need to have an RO_GSCVD section in their FMAP, and production boards should override the CONFIG_VBOOT_GSC_BOARD_ID option with the correct ID for each variant. BUG=b:229015103 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1cf86e90b2687e81edadcefa5a8826b02fbc8b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-21mb/google/nissa: Create pujjo variantStanley Wu
Create the pujjo variant of the nissa reference board by copying the template files to a new directory named for the variant. (Follow other ADLN variant to generate by manual) BUG=b:235182560 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJO Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I73ec985bc19320260d0c3132c1ca23a3648df9e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-17mb/google/nissa: Create joxer variantMark Hsieh
Create the joxer variant of the nissa reference board by copying the template files to a new directory named for the variant. BUG=b:236086879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_JOXER Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4cb74f90c4ec33818b551d5f51759930e3222677 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2022-06-10mb/google/brya: Select SOC_INTEL_RAPTORLAKE for skolas variantsBora Guvendik
BUG=b:229134437 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib0531ff736ed7ac52bff8607b26b3e7f1d3ac3ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-09mb/google/brya: Create ghost4adl variantJack Rosenthal
Create new variant of Brya "ghost4adl". Memory config and device tree was sourced from the schematics (revision 7670d041f40279b5126990f20ec8f90c0538440c). GPIO overrides have not been added yet. This is to be added in a follow-on CL. BUG=b:234626939 BRANCH=firmware-brya-14505.B TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-06-02mb/google/brya: Add new skolas baseboardNick Vaccaro
This commit adds the skolas baseboard, which is basically the brya baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder Lake SoC. This commit also adds the skolas baseboard variant skolas4es. Since this baseboard is identical to the brya baseboard with the exception of the SoC used, the new baseboard and the new baseboard's first variant will be a copy of the current brya baseboard and brya0 variant. For now, the skolas baseboard and skolas4es variant will continue to use ADL-P. This allows for two benefits: 1. software to be proven out on existing hardware prior to RPL SoC support landing, and 2. allows us not to have to wait for RPL SoC changes prior to getting the mainboard changes in place Once the RPL SoC code has merged, I will update the skolas baseboard and skolas4es variant to use RPL instead of ADL. BUG=b:229134437 TEST=util/abuild/abuild -p none -t google/brya -x -a -c max Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-31mb/google/nissa: Add and default to 16 MB layoutKangheui Won
Future nissa devices will mostly use 16MB SPI flash. Add 16MB layout and make it default for nissa. BUG=b:202783191 TEST=build nissa and brya firmware, check they're still 32MB Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I04ae46d62d3e018610ca2533c186dda980bd67bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-29mb/google/brya: Increase Resizable BAR address space limit to 32 bitsTim Wawrzynczak
The dGPU used for some Brya projects requests 32 bits of address space for one of its BARs via the Resizable BAR mechanism. This Kconfig is currently set at 29 bits for brya, so the allocation currently is capped at 29 bits. This patch sets the limit to 32 bits for brya boards, which is enough for the GPU. BUG=b:214443809 TEST=all of the dGPU PCI BARs on agah can be successfully allocated Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I61dbe47f1f316967d052bae748ff23babde61ef0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-24mb/google/brya: Set eMMC dll tuning parameters for NissaUsha P
Add support for MB level dll tuning. This patch sets the eMMC dll tuning parameters to default values needed. There was issue observed on some eMMC devices which failed to boot in HS400 mode.EV team suggested the intermediate eMMC dll tuning parameters that needs to be set. We observed these values helped to fix the issue. While we get the verified default values set from FSP directly, adding it here to use it as the custom dll values needed. BUG=b:230403441 TEST=Build and boot nivviks board. Verify the eMMC dll parameters are overridden. [INFO ] usha: After override dll_params [INFO ] usha: emmc_tx_cmd_cntl=505 [INFO ] usha: emmc_tx_data_cntl1=909 [INFO ] usha: emmc_tx_data_cntl2=1c2a2828 [INFO ] usha: emmc_rx_cmd_data_cntl1=1c1b1d3c [INFO ] usha: emmc_rx_cmd_data_cntl2=10049 [INFO ] usha: emmc_rx_strobe_cntl=11515 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I27771b663ce9808e5a5ef4b36c136ad78f924376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-24mb/google/brya: Create kuldax variantDavid Wu
Create the kuldax variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:233380254 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KULDAX Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I95c04768bbed8657d2858bcd66fc041f56910b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-20mb/google/brya: Add PEG and initial Nvidia dGPU ASL supportTim Wawrzynczak
Some brya variants will use a GN20 series Nvidia GPU, which requires quite a bit of ACPI support code to be written for it. This patch lands a decent bit of the initial code for it on the brya platform, including: 1) PEG RTD3 methods 2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods) 3) NVOP _DSM method There will be more support to come later, this is all written to specifications from the Nvidia Software Design Guide for GN20. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-17mb/google/brya/var/mithrax: update overridetree and KconfigJohn Su
1. Update override devicetree based on schematics. 2. Update Kconfig based on schematics. BUG=b:229191897 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ia28ae16f609fda6d90558e69b2d41139dbe533fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-16drivers/i2c/tpm: Work around missing firmware_version in Ti50 < 0.0.15Reka Norman
Ti50 firmware versions below 0.0.15 don't support the firmware_version register and trying to access it causes I2C errors. Some nissa boards are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading the firmware version and select it for nissa. The firmware version is only read to print it to the console, so it's fine to skip this. This workaround will be removed once all ODM stocks are updated to 0.0.15 or higher. A similar workaround Kconfig was added in CB:63011 then removed in CB:63158 which added support for separate handling of Cr50 and Ti50. But we actually still need this workaround until all Ti50 stocks are upgraded to 0.0.15 or higher. BUG=b:224650720 TEST=Boot to OS on nereid with Ti50 0.0.14 Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-04mb/google/brya: Add EC mux device to brya0Prashant Malani
Add entries to the devicetree override for brya0 and enable the Kconfig to ensure the Chrome OS EC Mux driver is build tested. BUG=b:208883648 TEST=None BRANCH=None Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532 Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-28mb/google/brya: disable early EC sync for nereidPeter Marheine
The ITE EC used on Nereid can take a long time to update, and especially too long to erase. There is a 1 second timeout enforced on the EC erase command, but Nereid's IT81302 will typically take about 5 seconds to complete erase, and could take as long as 30. Since this affects any Nissa variant using an ITE EC and it's nice to make the entire Nissa project consistent, this change disables early sync for all Nissa boards. BUG=b:222987250 TEST=EC software sync is no longer attempted (and thus does not fail) on Nereid. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I55d36479e680c34a8bff65776e7e295e94291342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2022-04-24mb/google/brya: Create mithrax variantJohn Su
Create the mithrax variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:223091246 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MITHRAX Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7c2fa6a74cc8e37397dea7e67e8cfa6506a49bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-24tpm: Allow separate handling of Google Ti50 TPMJes Klinke
A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. This change makes use of Kconfigs TPM_GOOGLE_CR50 and TPM_GOOGLE_TI50 to be able to take slightly different code paths, when e.g. evaluating whether TPM firmware is new enough to support certain features. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/google/brya: Create osiris variantDavid Wu
Create the osiris variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:229352299 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OSIRIS Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I41e088a3415add86cba87c919af23494f816bb24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63650 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/google/brya/var/brya0: Swap TPM and touchscreen I2C busAmanda Huang
Based on the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:202671753 TEST=emerge-brya coreboot Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-19mb/google/brya: Add Kconfig for TPM I2C busRaihow Shi
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:229200525 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brya/var/crota: Kconfig: Select TPM I2C bus driverTerry Chen
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:226315394 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-13mb/google/brya: Create craask variantTyler Wang
Create the craask variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:None BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CRAASK Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Icf03e3f18468d7dd207ab200fa2dcf96afd02f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06mb/google/brya: Enable dynamic debug capability for brya familySridhar Siricilla
The patch enables dynamic debug capability for Brya family of boards. BRANCH=MAIN BUG=b:153410586 TEST= Verified the CSE firmware update functionality on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-03-25mb/google/brya: Adjust FMD file to chromeos.fmd for kanoDavid Wu
The separate FMD file for Kano is no longer required, as it was only required for early prototype testers, and those devices will be retired soon, therefore switch back to the original FMD file. BUG=b:226018550 TEST=Build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15Eric Lai
Ti50 FW under 0.15 is not support board cfg command which causes I2C errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed. Add workaround for the old Ti50 chip. BUG=b:224650720 TEST=no I2C errors in coreboot. [ERROR] cr50_i2c_read: Address write failed [INFO ] .I2C stop bit not received Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-21mb/google/brya: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTORSridhar Siricilla
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig which updates PMC settings in the IFD for Alder Lake A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is locked in the production systems, so the Kconfig is deselected. BUG=b:190588098 BRANCH=firmware-brya-14505.B TEST=Build the coreboot for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17mb/google/brya: Remove Pcie Generic driver for WWANCliff Huang
This was to merge PCIe ACPI code to WWAN device. But, now use recent _DSD generation changes in FM driver instead. PCie generic driver is not used for WWAN at this time. Also, RTD3 devices are moved to overridetree.cb where WWAN is present. BUG=b:221250331 BRANCH=firmware-brya-14505.B TEST= Check that _DSD is added to WWAN device in SSDT for the variants. Check that RTD3 is added to WWAN device in SSDT for the variants. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09mb/google/nissa: Add fmd file for nissaKrishna Prasad Bhat
Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash layout for brya is of 32MB size, and nissa is expected to have 16MB SPI NOR flash. The current composition of AP firmware exceeds 16MB. To get an estimate of the unutilized region in the current flash layout for nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware size to under 16MB and to remove the RW_UNUSED regions from the final fmd file. Below table gives the size reduction from brya fmd to nissa fmd: +----------------+-------------------+---------------+ | Region | Earlier size (KB) | New size (KB) | +================+===================+===============+ | SI_ME | 5116 | 3772 | +----------------+-------------------+---------------+ | RW_SECTION_A/B | 8192 | 4344 | +----------------+-------------------+---------------+ | VBLOCK_A/B | 64 | 8 | +----------------+-------------------+---------------+ | ME_RW_A/B* | 3008 | 1434 | +----------------+-------------------+---------------+ | RW_LEGACY | 2048 | 1024 | +----------------+-------------------+---------------+ | RW_ELOG | 16 | 4 | +----------------+-------------------+---------------+ | SHARED_DATA | 8 | 4 | +----------------+-------------------+---------------+ | VBLOCK_DEV | 8 | 0 | +----------------+-------------------+---------------+ | RW_SPD_CACHE | 4 | 0 | +----------------+-------------------+---------------+ | RW_NVRAM | 24 | 8 | +----------------+-------------------+---------------+ | WP_RO | 8192 | 4096 | +----------------+-------------------+---------------+ | GBB | 448 | 12 | +----------------+-------------------+---------------+ *Based on LZMA compression on ME_RW_A/B regions. With LZMA compression, this region can be 1434K. Without this, ~665K will be more in each of these regions. Patch: https://review.coreboot.org/c/coreboot/+/62358/ BUG=b:202783191 BRANCH=None TEST=Build and boot Nivviks. Cq-Depend: chrome-internal:4584911 Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-09mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW KconfigKrishna Prasad Bhat
Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>