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path: root/src/mainboard/google/brya/Kconfig
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2021-07-12mb/google/brya: Create kano variantDavid Wu
Create the kano variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:193052432 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KANO Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/brya: Create redrix variantWisley Chen
Create the redrix variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192052098 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_REDRIX Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-28mb/google/brya: Update mainboard properties for BB retimer upgradeMaulik V Vaghela
This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:54292 BUG=b:186521258 TEST=Updated BB retimer FW from 3.4 to 3.5 without any device connected. Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-14mb/google/brya: Create gimble variantMark Hsieh
Create the gimble variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:190334274 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GIMBLE Change-Id: If425571d95b3b20910f890428fb5726ebad2fdf4 Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55300 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12mainboard/google/brya: Enable software syncBoris Mittelberg
This change removes the GBB flag that disables SW sync BUG:184229267 TEST:manually running chromeos-firmwareupdate Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ie8b759a0cdb0c3a0a6458f64c16216459f076e27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55400 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04mb/google/brya: Add firmware configuration probing for audioSugnan Prabhu S
For all of the audio devices in overridetree.cb add the probe matches that will determine if the device should be enabled or not based on the selected audio daughter board type. AUDIO=MAX98357_ALC5682I_I2S: enable max98357, dmic1 and alc5682i AUDIO=MAX98373_ALC5682_SNDW: enable max98373, dmic2 and alc5682 BUG=b:188696010 TEST=test different audio devices based on fw_config value: > AUDIO=UNKNOWN ectool cbi set 6 0x00000000 4 2 > AUDIO=MAX98357_ALC5682I_I2S ectool cbi set 6 0x00000100 4 2 > AUDIO=MAX98373_ALC5682_SNDW ectool cbi set 6 0x00000200 4 2 Change-Id: I6f159442516830f9d304d78c83f070e4fcff4a37 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-03mb/google/brya: Create primus variantScott Chao
Create the primus variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0) BUG=b:188272162 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PRIMUS Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I26787f296793b281b7f1ee1a7d240006163c6015 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/brya: Add the first FW_CONFIG fields to brya0Tim Wawrzynczak
1) USB sub-board 2) SD sub-board 3) GSC 4) Keyboard backlight 5) Audio sub-board 6) LTE module Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I74ca5ab5366a17e9e1784ec872b9cd77f8663c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54097 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13mb/google/brya: enable DPTF functionality for bryaSumeet R Pawnikar
Enable DPTF functionality for Alder Lake based brya BRANCH=None BUG=b:188028732 TEST=Built and tested on brya board Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-30mb/google/brya: select GOOGLE_SMBIOS_MAINBOARD_VERSIONZhuohao Lee
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:186721096 TEST=1. emerge-brya coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Change-Id: I8eeb958f73607afb801794f91fbf91ec7bd5cd8b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-30mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBIEric Lai
Brya uses CBI to store dram part number. So enable the config. BUG=b:186571840 BRANCH=none TEST=dmidecode -t 17 can show the dram part number. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-26mb/google/brya: Enable GL9755 SD card readerEric Lai
Enable GL9755 SD card reader. BUG=b:185397257 TEST=SD card is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-14mb/google/brya: Enable CSE Lite SKUTim Wawrzynczak
The first CSE Lite SKU is available, therefore enable the Kconfig option to have the CSE reboot the system into its RW FW during a cold boot. BUG=b:183826781 TEST=50 cold reboot cycles Cq-Depend: chrome-internal:3758108 Change-Id: Ib3a1a9f8ac51bdab8858b2764d5bc0f6f07987cc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-08mb/google/brya: Add Board and SKU ID support from Chrome ECTim Wawrzynczak
BUG=b:180456030 TEST=`mosys` is able to detect the platform correctly Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifbaa4a380bdb546bb54d579b46fe5760b2f4b754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-06mb/google/brya: Fix MAINBOARD_PART_NUMBERFurquan Shaikh
This change updates MAINBOARD_PART_NUMBER string to use uppercase for first character. This matches what all others boards do. BUG=b:180456030 Change-Id: I10eaeef5ec662a5718b787a3f0e3705cf70d751d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51297 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05mb/google/brya: brya0: Add ACPI support for Type-C portsTim Wawrzynczak
BUG=b:181160586, b:181843816 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51258 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/brya: Fix a few mistakes in brya0 overridetreeTim Wawrzynczak
1) Both SAR sensors had a UID of `2`, making them indistinguishable 2) No `device` underneath max98357a `chip` Change-Id: Icf586229532819a7779652cbee73755b036dfbdc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27mb/google/brya: add HAS_RECOVERY_MRC_CACHE flagEric Lai
Brya’s chromeos.fmd contains a region for RECOVERY_MRC_CACHE, but does not select HAS_RECOVERY_MRC_CACHE, so it’s unused. BUG=b:174266035 TEST=Check MRC cache can allocate in recovery mode. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6b83eec3dcf27bafde610a701e55f1371a5d4571 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51081 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/brya: Enable cr50 supportTim Wawrzynczak
Add Kconfig options and devicetree entries for cr50 TPM. BUG=b:180017621 TEST=verify (via console) successful cr50 communications in verstage and payload (depthcharge). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-04mainboards: Remove default CHROMEOS=yKyösti Mälkki
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested with CHROMEOS=n. Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28mb/google/brya: Add variants overridetree.cb path and remove unused registersEric Lai
Add variants overridetree.cb path remove unused registers BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2940332044aa4c2de6d58f5d0d2a2a7c1b2c3478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-27mb/google/brya/var/brya0: Use auto-generated Makefile.incAmanda Huang
This change adds mem_list_variant.txt that contains the only memory parts used by brya0 for Proto-0 build and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. BUG=b:176491791 Change-Id: I3fe755564e7541a7abdfca0e5aa7fd786f5ca880 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-12mb/google/brya: Initialize overridetree.cbEric Lai
Initiate overridetree.cb based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I31e5ac1703476083ac71dac30b0a3299b38384c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Set UART consoleEric Lai
Follow latest schematic UART_PCH_DBG is UART 0. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48070 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Enable ACPI and add ACPI tableEric Lai
Enable ACPI configuration and add DSDT ACPI table. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/brya: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock and ramstage. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia658ab4b466242cf8658abb239f19a9c0a03849a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-22mb/google/brya: Add new google brya mainboardTim Wawrzynczak
This commit is a stub for brya, which is a an Intel Alder Lake-P reference platform. BUG=b:173562731 TEST=util/abuild/abuild -p none -t google/brya -a -c max Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia34130ff92a0a07063cb8e80527204b3a80184a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-18 23:59:04 +0000