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path: root/src/mainboard/google/brox
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2024-04-08mb/google/brox: Update verb table to fix headset detectionPoornima Tom
Correct verbtable value for pin widget 20 of Realtek ALC256 based on the updated verbtable received from Realtek. Updated Version : 5.0.3.1. This fixes the headset detection failure, when power_save is enabled in legacy hda driver. BUG=b:330433089 BRANCH=None TEST=Verified headset on Brox When connected to audiojack in power_save state of legacy hda driver, headset is detected and audio is resumed. Change-Id: I71b7d59b3ab5310a0b6cdb31fb5033f94263d151 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81654 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Terry Cheong <htcheong@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-04-02mb/google/brox: Enable PMC pins to work with PDAshish Kumar Mishra
Enable SMLINK1 interface for PMC-PD communication to configure Type-C muxes. Refer RPL EDS vol 1: 765585. BUG=b:327622474 BRANCH=None TEST=Boot image on SKU2 and check PMC-PD working. Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81207 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Deepti Deshatty <deepti.deshatty@intel.com>
2024-04-01mb/google/brox: Configure ISH device based on FW_CONFIGKarthikeyan Ramasubramanian
ISH Firmware name needs to be configured only when full sensing capabilities are enabled through ISH_ENABLE FW_CONFIG. Similarly DMA property needs to be added only when UFS is enabled through STORAGE_UFS FW_CONFIG. Hence configure the ISH device at run-time based on FW_CONFIG. BUG=b:319164720 TEST=Build Brox BIOS image and boot to OS. Change-Id: I678416acd48e03ab77ae299beae6e295a688b8df Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81418 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-30mb/google: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-03-27mb/google/brox: Fix GPE_EC_WAKE configurationKarthikeyan Ramasubramanian
Wake signal from EC is routed to GPP_D1 and hence GPE_EC_WAKE corresponds to GPE0_DW1_01. Fix GPE_EC_WAKE configuration. BUG=b:329026602 TEST=Build Brox BIOS image and boot to OS. Trigger suspend and wake up using EC generated events like AC connect/disconnect. Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
2024-03-21mb/google/brox: Configure I2C timing for I2C devicesIvy Jian
Configure I2C0/1 timing in devicetree to meet timing requirement. (THIGH(us) minimum is 0.6us). Before: I2C0 : THIGH(us) 0.595us I2C1 : THIGH(us) 0.582us After: I2C0 : THIGH(us) 0.673us I2C1 : THIGH(us) 0.666us Change-Id: I79af4fde4eb08d4eb896794756a633701bebb755 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81348 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-03-20mb/google/brox: support ISHLi Feng
Set FW_CONFIG bit 21 to enable ISH PCI device and define ISH main firmware name so ISH shim loader can load firmware from file system. ISH also need to be enabled if STORAGE_UFS is set. BUG=b:280329972 TEST= Set bit CBI FW_CONFIG bit 21 Boot Brox board, check that ISH is enabled and loaded lspci shows: 00:12.0 Serial controller: Intel Corporation Alder Lake-P Integrated Sensor Hub (rev 01). Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba Signed-off-by: Li Feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80773 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yuval Peress <peress@google.com>
2024-03-19mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSAshish Kumar Mishra
Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS in brox Kconfig. This enables a single binary for both SKU1 and SKU2. For SKU2, upon boot from cold reset, it will disable the UFS Controller and then trigger a warm boot. BUG=b:329209576 BRANCH=None TEST=Boot image on SKU1/SKU2 and check S0ix working. Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-15brox: ish: Add Kconfigs for ISHYuval Peress
Modeled after the Rex Kconfigs for ISH. Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Signed-off-by: Yuval Peress <peress@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81050 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13mb/google/brox: Enable EC SW SyncShelley Chen
Now that EC software sync has been verified to work on Brox, we can enable it by default. BUG=b:326152804 BRANCH=None TEST=Verify that SW sync occurs Change-Id: I3d356c006fc448125605761f7328d1f1e203a7c4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81211 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09mb/google/brox: Enable Wake on WLAN for SKU1Ashish Kumar Mishra
For SKU1, wake pin is WLAN_PCIE_WAKE_ODL. Update gpio config and corresponding ACPI for WoWLAN. BUG=b:327379404 BRANCH=None TEST=Boot image on SKU1 and check Wake on WLAN from S0ix. Change-Id: I04c35da2c9ac57cafdf7f7a35d83ab2e7a05fe4a Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-04mb/google/brox: Update Verbtable for beep functionalitypoornima tom
For boot beep functionality, relevant register values are required to be updated. BUG=b:324528901 BRANCH=None TEST=Build & verified Boot Beep functionality on Brox Change-Id: If236c8ac173a279db676af412377fa4e4122c1cd Signed-off-by: poornima tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80416 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-22mb/google/brox: Disable Early EC SyncShelley Chen
Early EC Sync does not need to be enabled in coreboot as EFS2 is being enabled in the EC. BUG=b:326152804 BRANCH=None TEST=emerge-brox coreboot To be tested with EC sync enabled Change-Id: I08bdbe9f3dcea837b0b148adc137c03d3461877a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80689 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20mb/google/brox: enable DPTF functionality for broxSumeet Pawnikar
Enable DPTF functionality for brox board BRANCH=None BUG=b:324360936 TEST=Built and tested on brox board Change-Id: I0315f7f45688ccc36d321d6be4fa4fac7559a16b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-18mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-17mb/google/brox: Handle bluetooth enable on devicesAshish Kumar Mishra
For devices that require CNVi Bluetooth select WIFI_BT_CNVI in FW_CONFIG. Discrete Bluetooth devices need to select WIFI_BT_PCIE. BUG=b:319188820,b:325084796 BRANCH=None TEST=Boot image on SKU1,SKU2 and check BT devices enumerate. Change-Id: Iba008682fcfa7ddc1ec400649c8742c721666f1d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80564 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-16mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPICShelley Chen
Setting the EC interrupt GPIO as an APIC is able to solve many problems that we are currently seeing: 1. Routing through the APIC make the IRQ# associated with this pin unavailable to claim for other devices in the kernel. This is causing EC interrupts to not work. 2. Since EC interrupt are not working, we are not able to flash the EC from the DUT. 3. Also, the GPI_INT configuration does not allow us to set the polarity of the GPIO, which means that it is by default set as active high. As a result, we are seeing an excessive number of host command interrupts to the EC. This disappears when we change the configuration to APIC and set the polarity as INVERT. BUG=b:319129926,b:324707182 BRANCH=None TEST=1. After boot up, check if ec_cros_lpcs driver was successfully registered. Look for the following string: "cros_ec_lpcs GOOG0004:00: Chrome EC device registered" 2. Make sure can flash the EC image from the DUT 3. Make sure EC console is not getting continuous stream of host commands. Change-Id: I74bff88d2ddbaf1f4b085c31d582bd66e18c438a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80467 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.corp-partner.google.com>
2024-02-13mb/google/brox: Set display output type for eDP panelMatt DeVillier
Set the display type for the LCD panel configured via the gfx/generic driver. This will ensure the correct DID/device address are generated in the SSDT. Change-Id: If63374329ed5eb4330517ca1bf2ba1ada24fa54a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80244 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-13mb/google/brox: Use name 'LCD0' for internal panel outputMatt DeVillier
The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. Change-Id: Id52f7c0e542423ba08eeed89bf9b171e540e10e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-09mb/google/brox: Initialize TCHSCR_RST_L to 0Shelley Chen
TCHSCR_RST_L signal was originally being configured to 1 in gpio.c but this was causing some leakage. Configuring it to 0 initially in romstage fixes this. Also, make sure that EN_PP3300_TCHSCR is initialized in romstage as well. BUG=b:322249892 BRANCH=None TEST=Make brox boots and touchscreen is still working Change-Id: I5bf1901a3a40a38237b950abcb758f96aebcc1cf Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80300 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-08mb/google/brox: Handle GPI_INT pin lower to GPI_WAKEAshish Kumar Mishra
In case where PAD_CFG_GPI_INT() is initialized with a pin value lower to PAD_CFG_GPI_IRQ_WAKE() for same GPIO community the set_ioapic_used() is only called for the PAD_CFG_GPI_IRQ_WAKE() pin. Due to this the IRQ associated with PAD_CFG_GPI_INT() is found free by find_free_unique_irq() during IRQ assignment and assigned to other pins which causes IRQ conflicts BUG=b:322984217 BRANCH=None TEST=Boot test on brox, check if correct IRQ assigned to EC Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80334 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-05mb/google/brox: Fix the I2C configurationKarthikeyan Ramasubramanian
Update the I2C configuration to match the usage such that only required I2C controllers are enabled. BUG=b:319390850 TEST=Build Brox BIOS image and boot to OS. Ensure that only the required I2C controllers are enabled. Change-Id: I9f24beb9ef587163362cc6ded88efb05be1329b9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80303 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-01mb/google/brox: Enable HDA Codec ALC256Poornima Tom
On Brox, HDA Codec used is ALC256. Add verb table for the same. Also, add the related device tree changes for HDA related registers. Realtek High Definition Audio Configuration- Version : 5.0.3.1 BUG=b:317398558 BRANCH=None TEST=verified HDA on Brox. HDA Sound cards detected. Headphone working verified. Device listed under sysfs as below: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ID 256 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Change-Id: I1edd5aee053debe39b34048266703031c088cd00 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79723 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26mb/google/brox: Enable TouchscreenShelley Chen
BUG=b:300690448,b:319393777 BRANCH=None TEST=tested on a device with i2cdetect Also tested with evtest and make sure Wacom is listed Change-Id: I4f528b0d778c8c4a4e83774d5c167ccb2d6afd9a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79895 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26mb/google/brox: Remove CNVi BluetoothShelley Chen
This is causing an assertion error on the devices that don't have CNVi enabled because CNVi is hidden behind a FW_CONFIG flag in the overridetree now. BUG=b:319188820 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage make sure we can boot to kernel on device. Change-Id: Ifcfbc04825d4d4e7f2874a4c52f9c5cf3e657856 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80211 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25mb/google/brox: Switch EC INT and WAKE GPIOsShelley Chen
There was a mistake in the gpio spreadsheet provided by the HW team and the GPIO assignments for the EC INT and WAKE signals got switched from what it was in the schematics. The correct assignments are: GPP_D0 = EC_PCH_INT_ODL GPP_D1 = EC_PCH_WAKE_ODL BUG=b:311450057,b:300690448 BRANCH=None TEST=emerge-brox coreboot Will try to boot OS image on device and see if there are any ec errors. Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79886 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/asurada to cyan: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5855f49984db59d786decad6142e3525b146a573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80105 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-23mb/google/brox: Move cnvi to overridetreeShelley Chen
We need to disable the cnvi device when pcie wifi is enabled, so need to use the FW_CONFIG defined in the overridetree for this. BUG=b:311450057,b:300690448,b:319188820 BRANCH=None TEST=This will be tested on the device when received Change-Id: If9e861db37e321fd69c09f9b4aafa2e212f92caa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79898 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-23mb/google/brox: Enable WLAN on root port 5Shelley Chen
BUG=b:311450057,b:300690448,b:319188820 BRANCH=None TEST=test on device with lspci & make sure can see the Intel Network controller Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-20mb/google/brox: enable WIFI_SARShelley Chen
Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG for WIFI to choose the right wifi_sar hex file. Below is the file mapping: wifi_sar_0.hex = wifi6 wifi_sar_1.hex = wifi7 BUG=b:319302319 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Change-Id: I212c80412141e7770a512bd8ccf4111963bab395 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80085 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/brya: Drop primus4es boardJakub Czapiga
Primus4es board is no longer supported thus drop it from the tree. TEST=Build all Brya boards in CrOS-SDK - Primus4ES not built. No negative impact observed. Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-18mb/google/brox: Fix user facing camera acronymShelley Chen
I got confused and used UFS (User Facing Side) for the User Facing Camera (UFC) in the FW_CONFIGs. Change references of the camera from UFS --> UFC. BUG=b:300690448 BRANCH=None TEST=None. The camera has not been enabled yet. Change-Id: I4f8240ae51aad1e077f325a9eab5a2a92f1402cb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79997 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17mb/google/brox: Move storage devices to overridetreeShelley Chen
These are specific to the brox board, so moving devices to the brox variant. BUG=b:311450057,b:300690448,b:319058143 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage will check if this helps detect the storage device in the factory Change-Id: I18d096040c293abfd4cd0b1bb5f50ba6dcc2e183 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-17mb/google/brox: Set up FW_CONFIGShelley Chen
Brox project has FW_CONFIG bits already set up in the project file for the retimer and for storage, so make sure that the brox device tree matches those settings. BUG=b:311450057,b:300690448,b:319058143 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage will check if this helps detect the storage device in the factory Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79854 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-13mb/google/brox: Enable Elan trackpadShelley Chen
BUG=b:311450057,b:300690448 BRANCH=None TEST=to be tested on a device with i2cdetect Change-Id: If6da1c722e87a50c6d422b300f16a52d884fa08f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-13mb/google/brox: Configure vGPIOs for NVMeShelley Chen
This is needed for NVMe to work when PCIe device is connected to the CPU side of RPL soc. BUG=b:311450057,b:300690448, b:319058143 BRANCH=None TEST=Tested on device and was able to boot to the OS Change-Id: Ic8a1fdcedf2ec6c7bf1dd00e02ef7c13e9338aac Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-13mb/google/brox: Disable package c state demotionShelley Chen
This needs to be disabled for RPL otherwise we'll hit the assertion: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', line 1066 There is a comment in the referenced file/line in the assertion that says that "C state demotion must be disabled for Raptorlake J0 and Q0 SKUs." So, disabling it. BUG=b:311450057,b:300690448 BRANCH=None TEST=Tested that we didn't hit this assertion on the device after this change Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79855 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-09mb/google/brox: Fix error in DDR DQS configShelley Chen
The DQS mapping for DIMM idx 6 was discovered to be incorrect to what was in the schematics. Correcting the mistake in this CL. BUG=b:311450057,b:300690448 BRANCH=None TEST=tested on device and it passed memory training Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-12-28mb/google/brox: Add new GFX devicesShelley Chen
Add GFX devices for DDI (eDP and HDMI) and TCP (USC C0 and C2 ports). Copied the PLD placements from USB PLDs. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: Ic39916819f64ede1c80eccfd05ba4916b9f285af Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-12-22mb/google/brox: Fix config errors with 8 GPIOsShelley Chen
Some GPIOs were not configured correctly according to the HW spreadsheet provided by the HW team. * GPP_B5/GPP_B6 use NF1, not NF2 * GPP_B23 should use NF2, no GPI * GPP_D11 should be set to NC * GPP_E21/22 should be using NF (previous NC) * GPP_F17 is a GPO * GPP_F18 should be an interrupt, not a NF BUG=b:300690448,b:316180020 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I9e1e62adb79bd7fdab935afdbf2d23f9061b88aa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-22mb/google/brox: Align GPIO reset with HW spreadsheetShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes in this CL are to fix the pad's reset field as needed. See "Intel SoCs" section in https://doc.coreboot.org/getting_started/gpio.html for reset definitions. BUG=b:300690448,b:316180020 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I4285136184c648adb9dc97748bd6b01cba3f8ddd Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-12-22mb/google/brox: Fix pulls as necessaryShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes in this CL include fixing the pulls for GPIOs as necessary, making sure that it matches what is in the HW team's spreadsheet. BUG=b:300690448 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: Ie50cb3c6fc85f1633c1afd1330c0e040e04b0ec1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79704 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22mb/google/brox: Change unused GPIOs to NCShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes here include changing the pad config to NC because it is not being used in ChromeOS. BUG=b:300690448 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I15471e4d7ff25c858b05ef024f15ca7c0b9e598e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79703 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-21mb/google/{brya,brox,rex}: Update ec_sync wake capabilityMark Hasemeyer
Some of the boards use the EC_SYNC pin to wake the AP but do not advertise the pin as wake capable in the CREC _CRS resource. Relevant boards were determined through empirical testing and inspection of gpio configuration. Update the ACPI tables for rex, brya, and brox based boards to advertise their EC_SYNC pin as wake capable. BUG=b:243700486 TEST=-Dump ACPI and verify ExclusiveAndWake share type is set when EC_SYNC_IRQ_WAKE_CAPABLE is defined -Wake Aviko via keypress and verify chromeos-ec as wake source -Wake Screebo via lid open and verify chromeos-ec as wake source Change-Id: I5828be7c9420cab6ae838272c8301c302a3e078c Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79374 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20mb/google/brox: Enable FSP UPD LpDdrDqDqsReTrainingIvy Jian
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:311450057 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I4a009076e50408a4f7ff16ddc96a0f2e47b09470 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79646 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-17mb/google/brox: Disable EC/PD SW SyncShelley Chen
For initial debugging, we want to disable SW syncing. Will re-enable in the future. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage run gbb_utility --get --flags <image> make sure that it returns 0xa39 Change-Id: I865e9585ab37d1328a0ff54c6343cdad2c02220c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79569 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Short <keithshort@chromium.org>
2023-12-13mb/google/brox: Generate RAM ID for supported memory partIvy Jian
Add the MICRON MT62F1G32D2DS-023 WT:B RAM part for brox: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-023 WT:B 2 (0010) BUG=b:311450057,b:315913909 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Id120a5eb311d8299a8e59d2c1658fe0742e93934 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-08mb/google/brox: Update configuration for USB portsIvy Jian
Update brox devicetree based on the latest schematics. - Configure typeC to EC mux ports settings. - Configure USB2/USB3 ports settings. - Configure TCSS ports settings. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: Iac5a2e8be6cea64f107d267d4cf71529f08bb63d Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79391 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06mb/google/brox: Generate RAM IDs for two modulesIvy Jian
Add the support LP5 RAM parts for brox: 1. HYNIX LPDDR5 6400 2GB H9JCNNNBK3MLYR-N6E 2. MICRON LPDDR5 6400 4GB MT62F1G32D4DR-031 WT:B DRAM Part Name ID to assign H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:311450057 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Ib17f26a310435e37088191594863a645aa751440 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79392 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-12-05mb/google/brox: Fix memory configShelley Chen
Fix up the memory config for brox based on the schematics. Also, since memory training needs to happen in romstage, initializing the MEM_STRAP & MEM_CH_SEL gpios for use in romstage. Also consolidating the GPIOs needing to be initialized in romstage into the baseboard gpio.c file. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-12-01mb/google/brox: Update storage settings for SSD and UFSIvy Jian
Brox has SSD and UFS storage per different SKU. 1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio settings according to the schematic. 2. Enable UFS, also enable ISH since it is PCI function 0, required for UFS function 7 to be enabled. 3. Set unused SRCCLKREQ signals to NC. 4. Remove unused gpio settings in variant gpio table to prevent unexpected overrides. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-29mb/google/brox: Fix configuration for TPMShelley Chen
On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to reflect this. Also, fixing up the TPM entry in the device tree. Making sure that the GPIO for GSC_PCH_INT_ODL is set correctly. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79102 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-11-18mb/google/brox: Use Ti50 configShelley Chen
Brox is using Ti50, so make sure that we set the right config for that. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18mb/google/brox: Fix GPIO assignments in gpio.hShelley Chen
Assigning the macros in gpio.h to the correct GPIOs. Also, fixing GPE configurations so that they are mapped to the proper wake sources (GPP_B, D, E groups). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-14mb/google/brox: Set unstuffed straps to NCShelley Chen
All of these signals have net names, but are actually unstuffed, so we have to set them to NC. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I27d8b7cd02aefb49a2dc031a30eb0d1e8aa9faa9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-11-13mb/google: Remove obsolete Kconfig symbol VBT_DATA_SIZE_KBMartin Roth
The symbol VBT_DATA_SIZE_KB was removed in commit 8bde652241 - "drivers/intel/gma/opregion: Use CBFS cache to load VBT" CB:77886, however that patch only removed the Kconfig option from the Intel chipsets, leaving it unused in the mainboards. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia29d8d6ec17b172e662ff591849f1668d65f1ff9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78967 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-09mb/google/brox: Remove use of EC_IN_RW_OD GPIOShelley Chen
Later GSCs don't need a EC_IN_RW GPIO anymore, so removing the use of this for get_ec_is_trusted(). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I29f94969e9f2c1f239d9f9655f39b8410296f695 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-11-08mb/google/brox: Configure early GPIOs in bootblockShelley Chen
Some GPIOs (like WP and GSC) need to be configured in bootblock. Making sure that they get configured earlier for this. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8dd4853bc05b954f47d858d87ea2aed48e4b8074 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78943 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-08mb/google/brox: Correcting GPIOs based on latest schematicsShelley Chen
There are some inaccuracies in arbitrage. This is the first pass at correcting the incorrectly generated configs. I also tried to update the "No heuristic was found useful" comment generated by arbitrage into something more useful (ie: the appropriate NFs). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I836565e09a3e0b25746b3e2f9ed6610eaacf7e97 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78942 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01mb/{google,intel}: Update FMD to support CBFS verificationAnil Kumar
This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed for boards that currently use them. BUG=b:284382452 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-10-26mb/google/brox: Add Arbitrage generated gpio.c fileShelley Chen
Checking in gpio.c generated by arbitrage. Used this command line to generate: arb export-coreboot-gpio --refdes=U1 brox:proto1_20231017 BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I1098bd4cfde393ed9e78cd90158c3534fdf0dc09 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78657 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26mb/google/brox: use Alderlake-P SoC instead of Alderlake-SShelley Chen
Skolas is actually using the SOC_INTEL_ALDERLAKE_PCH_P config, so fixing Brox to reflect this as it's using the same SoC. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I632ec055d523956983d2053cd8e7000b1eaabf92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78656 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-18mb/google/brox/Kconfig: Don't redefine config optionFelix Singer
Commit 9b230ae2955 introduced a redefinition of the config option `BOARD_GOOGLE_BROX`, which is already defined in Kconfig.name accordingly and thus causing a Kconfig warning. Fix that by removing the type redefinition. Change-Id: Iea6219a686a23d8d48a0bfb6ac642efd482fded9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78394 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-13mb/google/brox: Create new Brox baseboardShelley Chen
This CL is just getting the initial brox framework to get the baseboard building. Copied files from brask baseboard and tried to remove contents of some files like the device tree and memory IDs. Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to DRAM ID 0. BUG=b:300690448 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 22:25:46 +0000