coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2024-08-14	mb/google/brox: Remove Mainboard Prepare to Sleep(MPTS) ACPI method	Karthikeyan Ramasubramanian
	Brox does not have PCIe WWAN or discrete GPU. Hence no need to power them off during suspend. Hence also remove the MPTS ACPI method. BUG=None TEST=Build Brox firmware and boot to OS. Change-Id: Ia239c3f038ce31934efb0a391350fa0f786e3fcd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83788 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-13	mb/google/brox: Do not override GPIO PM	Karthikeyan Ramasubramanian
	Brox uses Ti50 which always supports long interrupt pulse. Hence no need to override GPIO PM. BUG=None TEST=Build Brox firmware and boot to OS. Perform suspend/resume for 25 cycles. Change-Id: I6a138c1953714bc29570db587594cab8f315a4ec Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83856 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30	mb/google: Remove blank lines before '}' and after '{'	Elyes Haouas
	Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-31	device/device.h: Rename busses for clarity	Arthur Heymans
	This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-13	mb/google/brox: Create new Brox baseboard	Shelley Chen
	This CL is just getting the initial brox framework to get the baseboard building. Copied files from brask baseboard and tried to remove contents of some files like the device tree and memory IDs. Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to DRAM ID 0. BUG=b:300690448 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>