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path: root/src/mainboard/google/brox/Kconfig
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2024-08-05mb/google/brox: Add model brox-ti-pdcBob Moragues
BRANCH=None BUG=b:348171026 TEST=Test on TI PDC device Cq-Depend: chromium:5691079 Cq-Depend: chromium:5691080 Cq-Depend: chrome-internal:7464767 Original-Change-Id: I6ffb8bdb2245a74b0d5270435d0ffc8a44e7c2a6 Original-Signed-off-by: Bob Moragues <moragues@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5691110 Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Change-Id: Iac5b4cd4dcb1d274553f78e9d4295f8f9ad8a863 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-08-01mb/google/brox: Create jubilant variantRen Kuo
Create the jubilant variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:348543712 TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_JUBILANT. Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83212 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2024-07-05mb/google/brox/var/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSWentao Qin
SKU1 is UFS, SKU2 is NON-UFS, it needs to select this config to disable the MPHY clock in the SKU2 configuration to ensure that S0ix functions normally. BUG=b:350609955 BRANCH=None TEST=Boot image on SKU1/SKU2 and check S0ix working. Change-Id: I2fbcc7ffaabf3c085a3345ec94a8d45b225b3450 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-26mb/google/brox/lotso: Add Fn key scancodeWen Zhang
The Fn key on Lotso emits a scancode of 94 (0x5e). BUG=b:322721490 TEST=Flash Lotso, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I999627f0ea9db1d79376150a04920ac877a48447 Signed-off-by: Wen Zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83204 Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-28mb/google/brox: Add romstage early graphicsSowmya Aralguppe
Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image. This patch enables Sign of Life image during MRC training. BUG=b:335369811 TEST=Able to boot to ChromeOS with SOL image. CPU log: [SPEW ] bootmode is set to: 0 (boot with full config) [0.384818] DP PHY mode status not complete [0.388911] DP PHY mode status not complete [0.393197] DP PHY mode status not complete [0.397484] DP PHY mode status not complete [0.401771] DP PHY mode status not complete [0.406057] DP PHY mode status not complete [0.410345] DP PHY mode status not complete [0.414632] DP PHY mode status not complete [0.418916] DP PHY mode status not complete [0.423203] DP PHY mode status not complete [0.427491] DP PHY mode status not complete [0.431777] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. [DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes) [WARN ] CBFS: 'preram_locales' not found. [ERROR] ux_locales_get_text: preram_locales not found. [DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes) [INFO ] ELOG: NV offset 0xf20000 size 0x4000  elogtool list: 0 | 2024-05-10 02:26:07-0700 | Log area cleared | 4088 1 | 2024-05-10 02:26:07-0700 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2024-05-10 02:26:51-0700 | Memory Cache Update | Normal | Success 3 | 2024-05-10 02:27:09-0700 | System boot | 4 4 | 2024-05-10 02:27:09-0700 | Firmware Splash Screen | Enabled 5 | 2024-05-10 02:27:11-0700 | System Reset 6 | 2024-05-10 02:27:11-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2024-05-10 02:27:18-0700 | ACPI Enter | S5 8 | 2024-05-10 02:27:36-0700 | System boot | 5 9 | 2024-05-10 02:27:36-0700 | Firmware Splash Screen | Enabled 10 | 2024-05-10 02:27:37-0700 | System Reset 11 | 2024-05-10 02:27:37-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
2024-05-14mb/google/brox/var/greenbayupoc: Update devicetree and gpio settingsEren Peng
Based on latest schematics GREENBAY_0412.SCH update the gpio and devicetree settings. BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Cq-Depend:chrome-internal:7218819 Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455 Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-12mb/google/brox/var/greenbayupoc: Configure board for SODIMM useEren Peng
Configure SODIMM settings for greenbayupoc. The SODIMM settings are copied from mainboard/google/brya/variants/baseboard/brask/memory.c. BUG=b:336955026, b:332230842 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM. Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-09mb/google/brox: Sending End of Post (EOP) asynchronouslyKarthikeyan Ramasubramanian
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time. BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS. Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-06mb/google/brox:Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATIONKrishna Prasad Bhat
Brox uses PDC<->PMC direct connection for USBC mux configuration. Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. This patch also adds additional dependency on ENABLE_TCSS_USB_DETECTION to be selected only when PDC<->PMC direct connection and CHROMEOS is not used. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-04-30soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZEFelix Singer
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-19mb/google/brox: Create lotso variantKun Liu
Create the lotso variant of the brox reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:333494257 BRANCH=None TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_LOTSO Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-04-15mb/google/brox: Create greenbayupoc variantEren Peng
Create the greenbayupoc variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:329530883 BRANCH=None TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_GREENBAYUPOC. Change-Id: I90936d97b41e59c49dd92997146caf580bce1f4f Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-19mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSAshish Kumar Mishra
Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS in brox Kconfig. This enables a single binary for both SKU1 and SKU2. For SKU2, upon boot from cold reset, it will disable the UFS Controller and then trigger a warm boot. BUG=b:329209576 BRANCH=None TEST=Boot image on SKU1/SKU2 and check S0ix working. Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-15brox: ish: Add Kconfigs for ISHYuval Peress
Modeled after the Rex Kconfigs for ISH. Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Signed-off-by: Yuval Peress <peress@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81050 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13mb/google/brox: Enable EC SW SyncShelley Chen
Now that EC software sync has been verified to work on Brox, we can enable it by default. BUG=b:326152804 BRANCH=None TEST=Verify that SW sync occurs Change-Id: I3d356c006fc448125605761f7328d1f1e203a7c4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81211 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-22mb/google/brox: Disable Early EC SyncShelley Chen
Early EC Sync does not need to be enabled in coreboot as EFS2 is being enabled in the EC. BUG=b:326152804 BRANCH=None TEST=emerge-brox coreboot To be tested with EC sync enabled Change-Id: I08bdbe9f3dcea837b0b148adc137c03d3461877a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80689 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-01mb/google/brox: Enable HDA Codec ALC256Poornima Tom
On Brox, HDA Codec used is ALC256. Add verb table for the same. Also, add the related device tree changes for HDA related registers. Realtek High Definition Audio Configuration- Version : 5.0.3.1 BUG=b:317398558 BRANCH=None TEST=verified HDA on Brox. HDA Sound cards detected. Headphone working verified. Device listed under sysfs as below: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ID 256 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Change-Id: I1edd5aee053debe39b34048266703031c088cd00 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79723 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-20mb/google/brox: enable WIFI_SARShelley Chen
Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG for WIFI to choose the right wifi_sar hex file. Below is the file mapping: wifi_sar_0.hex = wifi6 wifi_sar_1.hex = wifi7 BUG=b:319302319 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Change-Id: I212c80412141e7770a512bd8ccf4111963bab395 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80085 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/brya: Drop primus4es boardJakub Czapiga
Primus4es board is no longer supported thus drop it from the tree. TEST=Build all Brya boards in CrOS-SDK - Primus4ES not built. No negative impact observed. Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-17mb/google/brox: Disable EC/PD SW SyncShelley Chen
For initial debugging, we want to disable SW syncing. Will re-enable in the future. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage run gbb_utility --get --flags <image> make sure that it returns 0xa39 Change-Id: I865e9585ab37d1328a0ff54c6343cdad2c02220c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79569 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Short <keithshort@chromium.org>
2023-12-01mb/google/brox: Update storage settings for SSD and UFSIvy Jian
Brox has SSD and UFS storage per different SKU. 1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio settings according to the schematic. 2. Enable UFS, also enable ISH since it is PCI function 0, required for UFS function 7 to be enabled. 3. Set unused SRCCLKREQ signals to NC. 4. Remove unused gpio settings in variant gpio table to prevent unexpected overrides. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-29mb/google/brox: Fix configuration for TPMShelley Chen
On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to reflect this. Also, fixing up the TPM entry in the device tree. Making sure that the GPIO for GSC_PCH_INT_ODL is set correctly. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79102 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-11-18mb/google/brox: Use Ti50 configShelley Chen
Brox is using Ti50, so make sure that we set the right config for that. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-13mb/google: Remove obsolete Kconfig symbol VBT_DATA_SIZE_KBMartin Roth
The symbol VBT_DATA_SIZE_KB was removed in commit 8bde652241 - "drivers/intel/gma/opregion: Use CBFS cache to load VBT" CB:77886, however that patch only removed the Kconfig option from the Intel chipsets, leaving it unused in the mainboards. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia29d8d6ec17b172e662ff591849f1668d65f1ff9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78967 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-26mb/google/brox: use Alderlake-P SoC instead of Alderlake-SShelley Chen
Skolas is actually using the SOC_INTEL_ALDERLAKE_PCH_P config, so fixing Brox to reflect this as it's using the same SoC. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I632ec055d523956983d2053cd8e7000b1eaabf92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78656 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-18mb/google/brox/Kconfig: Don't redefine config optionFelix Singer
Commit 9b230ae2955 introduced a redefinition of the config option `BOARD_GOOGLE_BROX`, which is already defined in Kconfig.name accordingly and thus causing a Kconfig warning. Fix that by removing the type redefinition. Change-Id: Iea6219a686a23d8d48a0bfb6ac642efd482fded9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78394 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-13mb/google/brox: Create new Brox baseboardShelley Chen
This CL is just getting the initial brox framework to get the baseboard building. Copied files from brask baseboard and tried to remove contents of some files like the device tree and memory IDs. Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to DRAM ID 0. BUG=b:300690448 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 20:46:20 +0000