coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-08-21	mb/google/asurada: Fixup BOOT_DEVICE_SPI_FLASH_BUS default value	CK Hu
	On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. The number here should be a virtual value as (SPI_BUS_NUMBER + 1). Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ibc269201a34968c8400d2235e8da2ecd88114975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-13	mb/google/asurada: Add new MT8192 mainboard "Asurada"	CK Hu
	The placeholder functions and build rules for generating a minimal firmware to run on MT8192 SOC based mainboard "Asurada". Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>