summaryrefslogtreecommitdiff
path: root/src/mainboard/google/asurada/mainboard.c
AgeCommit message (Collapse)Author
2021-02-21mb/: Drop the provided name in chip_opsKyösti Mälkki
Little point to replicate a string already provided both as a global Kconfig and global mainboard_part_number. Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2021-01-08mb/google/asurada: Support audioTzung-Bi Shih
- Turns audio-related things power on. - Selects I2S pin-muxing. - Exposes GPIO "speaker enable" for switching on and off. BUG=b:176856418 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: If595657bbddad85bc9a154b3648bae1190cb00b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-17drivers: Replace set_vbe_mode_info_validPatrick Rudolph
Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple indepent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or fb_new_framebuffer_info_from_edid. Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-15mb/google/asurada: Initialize displayHuijuan Xie
Enable ANX7625 panel and configure display in mainboard_init() to support display in firmware screen. BUG=b:155713214 BRANCH=none TEST=Recovery screen is shown in recovery mode. Signed-off-by: Huijuan Xie <huijuan.xie@mediatek.corp-partner.google.com> Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/46578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-10soc/mediatek/mt8192: Init DPMHuayang Duan
DPM is a hardware module for DRAM power management and for better power saving in low power mode. BUG=none TEST=Boots correctly on Asurada Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/mediatek/mt8192: add spmfw loaderRoger Lu
This patch adds support for loading spm firmware from cbfs to spm sram. Spm needs its own firmware to enable spm suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. BUG=b:159079649 TEST=suspend with command `powerd_dbus_suspend` and wake up the DUT by powerkey Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-18mb/google/asurada: Configure pins mode for SDWenbin Mei
Configure the pins for SD to msdc1 mode and change the driving value to 8mA. Enable VCC and VCCQ power supply for SD. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I11151c659b251db987f797a6ae4a08a07971144b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-28mb/google/asurada: Pass reset gpio parameter to BL31CK Hu
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I2ae7684a61af76693605cc0bcf8d20c8992c7bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/46388 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28mb/google/asurada: Configure pinctrl for SD and MMCWenbin Mei
The pins for SD and MMC must be configured properly so we can access them in payloads. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Ie6bdffb987d5acf286645550f1c53f294f71c38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-12mb/google/asurada: Add USB supportCK Hu
Change-Id: I35dc4be65f0843c3c74695c443dd958676e6c12c Signed-off-by: CK Hu <ck.hu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-13mb/google/asurada: Add new MT8192 mainboard "Asurada"CK Hu
The placeholder functions and build rules for generating a minimal firmware to run on MT8192 SOC based mainboard "Asurada". Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 00:40:24 +0000