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The Asurada EC is using the large packet (256B) mode, and we were
seeing lots of timeout errors on various commands.
The AcceptTimeoutUs in EC SPI driver is hard-coded at 5000,
and that is too small for large packet running in 1M so we
should change EC SPI to the same value that kernel is using (3M).
BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46394
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs.
BUG=None
TEST=emerge-asurada coreboot; # also boots into emmc
BRANCH=None
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46386
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure and initialize EC and TPM on Asurada.
BUG=none
TEST=boot asurada
Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The placeholder functions and build rules for generating a minimal
firmware to run on MT8192 SOC based mainboard "Asurada".
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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