| Age | Commit message (Collapse) | Author |
|---|
|
The SKU ID for Asurada should come from AP ADC channel 5 and 6.
BUG=None
TEST=make; boots on asurada
Change-Id: I6a00c555f20aca4cd7f8bcee46ee81c17ef6ca3c
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
To reduce qualification effort, we want to pre-populate DRAM by their
size, package type and geometry so when a new DRAM is introduced we
don't need to spin off a new firmware release.
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I42ee170c159e551e840ab4e748f18f5149506b4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Asurada the RAM code can be
read from ADC channel 3.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The placeholder functions and build rules for generating a minimal
firmware to run on MT8192 SOC based mainboard "Asurada".
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
