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path: root/src/mainboard/google/asurada/Kconfig
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2021-03-09mb/google/asurada: Enlarge CONSOLE_CBMEM_BUFFER_SIZEYu-Ping Wu
Enlarge CONSOLE_CBMEM_BUFFER_SIZE from 128K (default) to 512K, so that more DRAM calibration logs can be stored in CBMEM console. BUG=b:181933863 TEST=emerge-asurada coreboot TEST="cbmem -c" shows the whole full calibration log BRANCH=none Change-Id: If82cbee5d2d5e97d98cbdaecda739d91a7cca0f8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51275 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25mb/google/asurada: Enable RTC for event logYu-Ping Wu
BUG=b:177399759 TEST=firmware_EventLog passed on asurada BRANCH=none Change-Id: I759f9030f525fa9e34ed542198a9dba8f25909f5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-28mb/google/asurada: Add config for spherionYu-Ping Wu
BUG=b:178440482 TEST=emerge-asurada coreboot BRANCH=none Change-Id: Ica09b73f97509db065c93c6be757c0d77c9b7a87 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-15mb/google/asurada: Initialize displayHuijuan Xie
Enable ANX7625 panel and configure display in mainboard_init() to support display in firmware screen. BUG=b:155713214 BRANCH=none TEST=Recovery screen is shown in recovery mode. Signed-off-by: Huijuan Xie <huijuan.xie@mediatek.corp-partner.google.com> Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/46578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-22mb/google/asurada: enable SPI devicesNicolas Boichat
Configure and initialize EC and TPM on Asurada. BUG=none TEST=boot asurada Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10mb/google/asurada: Add config for hayatoYu-Ping Wu
BUG=b:163789704 TEST=emerge-asurada coreboot BRANCH=none Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45163 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-21mb/google/asurada: Fixup BOOT_DEVICE_SPI_FLASH_BUS default valueCK Hu
On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. The number here should be a virtual value as (SPI_BUS_NUMBER + 1). Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ibc269201a34968c8400d2235e8da2ecd88114975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-13mb/google/asurada: Add new MT8192 mainboard "Asurada"CK Hu
The placeholder functions and build rules for generating a minimal firmware to run on MT8192 SOC based mainboard "Asurada". Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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