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In the end it does not look like RCBA register offsets are fully
compatible over southbridges.
This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.
Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.
Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.
This way libgfxinit also gets build-tested by Jenkins.
Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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TESTED Intel DG41WV with VGA, Intel DG43GT with VGA and HDMI1 and
HDMI2.
Change-Id: I774b79cc0ef9dc72ccf48901ab94376b27ed9c7a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Shuffle words and drop the _DATA_FILE suffix.
Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: If1f032d097224a1102ba29d8d45dce46aad3a91a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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These files are directly extracted from the vendor firmware.
Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I0b0a09098bd4185ae36f1468ebc151e39668ee86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Icae1983be6b8c5aebb121be8a383e2613e064122
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide empty stub implementations for set_pcie_reset() and
set_pcie_dereset(), many boards do not provide a proper one.
Change-Id: Ia6811442905ef1776fa5a8e3f5d4433e86e42f88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Callsite declared returning int, which makes more sense
than u8 the motherboard side code defined the functions
with.
Change-Id: I8ee83aa2833408ad163c9011a076e08578f3ca6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This change adds and updates headers in all of the mainboard files that
had missing or unrecognized headers. After this goes in, we can turn on
lint checking for headers in all mainboard directories.
Change-Id: Ibe038a8f7468253b21fd2ac90c045d0c9cc89dfc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.
Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tested with GRUB 2.02 as a payload, booting Arch Linux with
latest kernel. This code is based on the output of autoport
as well as existing ga-b75m-d3h and ga-b75m-d3v mainboards.
Working:
- Serial port I/O
- S3 suspend/resume (broken with SeaBIOS 1.11.1)
- USB ports and headers
- Gigabit Ethernet
- Integrated graphics (libgfxinit)
- PCIe x16 graphics
- PCIe x1
- SATA controller
- Hardware Monitor
- Fan Control (fancontrol on linux works well)
- Native raminit (4+4GB, 4+2GB, 2+2GB, DDR3-1333)
- Native graphics init with libgfxinit
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
- NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
tested with values different from the default.
Untested:
- VGA BIOS for integrated graphics init
- DVI port. It can detect a "fake" display, that is, an
EEPROM connected to the DVI port.
- PS/2 ports
- Audio: Only rear output (green) has been tested.
- EHCI debug.
- Parallel port
- Non-Linux OSes
- ACPI thermal zone and fan control (probably not working)
Not working:
- SATA devices with Tianocore (payload issue)
- PCIe to PCI bridge. It seems to be poorly supported on Linux,
it lacks a public datasheet and vendor BIOS behaves in the
same way: The bridge and the devices behind it appear, but
drivers fail to find devices attached to the bridge.
Change-Id: I598a0b75093a0f1aef2ac615035d66786a8c22cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Since the SIOW method doesn't use any arguments, don't pass it any,
and initialize it as not using any.
Change-Id: I3fa2ab8afb7d09c176a94bbd1db27587c36030cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use of device_t has been abandoned in ramstage.
Change-Id: I37ba054022241c93c03e6c804e46f4e8a1c1143e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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This change also makes sure that the sum the uma regions (TSEG, GSM,
GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between
2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR
setup for ramstage. At least tianocore requires this and fails to boot
without it.
Better MTRR are achieved by making the memory 'hole' till 4GiB exactly
2Gib.
This code mimics how it is done in nb/intel/gm45 and achieves similar
results.
TSEG is enabled and set to 8M since this makes it easier to reuse the
common smm setup / parallel mp code and makes it possible to cache the
ramstage in there like how it's done on newer targets.
TESTED on Intel DG43GT.
Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fix coding style
Change-Id: Id1c7104eb8520f20c826f5936029739a093d4dba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Many generations of Intel hardware have identical code concerning the
RCBA.
Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
Mainboards:
src/mainboard/a-trend/atc-6220
src/mainboard/a-trend/atc-6240
src/mainboard/abit/be6-ii_v2_0
src/mainboard/azza/pt-6ibd
src/mainboard/biostar/m6tba
src/mainboard/compaq/deskpro_en_sff_p600
src/mainboard/gigabyte/ga-6bxc
src/mainboard/gigabyte/ga-6bxe
src/mainboard/msi/ms6119
src/mainboard/msi/ms6147
src/mainboard/msi/ms6156
src/mainboard/nokia/ip530
src/mainboard/soyo/sy-6ba-plus-iii
src/mainboard/tyan/s1846
Change-Id: Id895963f9641bcaaa65e8a8cb21213a758a9ad80
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23301
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PNOT method never notifies the CPU to update it's _CST methods due
to reliance on inexisting variable (PDCx).
Add a method in the speedstep ssdt generator to notify all available
CPU nodes and hook this up in this file.
The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now
relies on code generated in the speedstep ssdt generator. CPUs not
using the speedstep code never included this PNOT method so this is
a logical place for this code to be.
Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Especially on ICH7 failing to do so results in i2c block read being
unusable. On ICH10 this problem doesn't manifest itself that much.
This moves disabling the watchdog reboot to the northbridge code like
i945 (even though it technically is southbridge stuff).
TESTED on Intel DG41WV: hacking on raminit is much nicer since no
need to do a hard power down for +4s are needed to clear the timeouts.
Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
(sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X.
This generates the main ACPI _PRT table automatically based on the
chipset registers.
Tested on Intel NUC DCP847SKE with Linux 4.13.14:
$ cat /proc/interrupts
CPU0 CPU1
0: 23 0 IO-APIC 2-edge timer
8: 1 0 IO-APIC 8-edge rtc0
9: 0 0 IO-APIC 9-fasteoi acpi
19: 86 0 IO-APIC 19-fasteoi ehci_hcd:usb1
23: 0 0 IO-APIC 23-fasteoi i801_smbus
[...MSI and other interrupts skipped...]
Log messages:
ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6
ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4
ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4
ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8
ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1
Generated _PRT:
Scope (\_SB.PCI0)
{
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
0x00000000,
0x00000015
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
0x00000000,
0x00000017
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
0x00000000,
0x00000010
}
})
}
Else
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKF,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKH,
0x00000000
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
}
})
}
}
}
Change-Id: I832a86925283d61b64b8268246d9e6f11994c120
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Removes rs780_before_pci_init() since it was a no-op anyway.
Removes get_nb_rev() since this function is provided via a macro in
the header.
This Makes a lot of function non-static since the header has
prototypes for these.
Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I6ee86396a1c5aaee248a275b42da801cedace586
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add a devicetree option to set temperature adjustment registers
required for thermal diode sensors and PECI. However, this commit does
not have the code needed to make PECI interface actually use these
registers. It only applies to diodes.
As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin
to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3".
PECI, apparently, takes precedence over diode, so the adjustment register
will be set and PECI activated. Or simply use the followup patch, which
makes THERMAL_PECI a mode like THERMAL_DIODE.
I don't have hardware to test THERMAL_DIODE mode, but in case of PECI,
without this patch I had about -60°C on idle. Now, with offset 97,
which was taken from vendor bios, PECI readings became reasonable 35°C.
TEST=Set a temperature offset, then ensure that the value you set is
reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset
Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Some of these will move to EARLY_CBMEM_INIT.
Change-Id: Ia969e30ad7097860180bd047eaf81859a42a747c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
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Remove obsolete code. The same settings are always done in southbridge.
Change-Id: Ic893ddbace73ae8b122c4fb675febc7d1e0b5da9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Note that all boards incorrectly had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Change-Id: I5e7890aafbc8c80716ee49690e306482a482a863
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20573
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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On this device libgfxinit successfully initializes textmode and
framebuffer mode on the device connected to the HDMI1 port.
VGA port is not tested, due to lack of VGA with valid EDID.
Every ports works on GNU/Linux with kernel version 4.9+80+deb9u1.
Due to limitations within the libgfxinit's current build system,
it needs "select NORTHBRIDGE_INTEL_IVYBRIDGE" to work, even it is
PCH instead of CPU for which libgfxinit should be configured here.
Change-Id: Ib1513fc57b79eebc5d047c2e24585731c44bc215
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change all 440BX boards to use the combined RAM init routine added in
commit 078e3240 (northbridge/intel/i440bx: Merge RAM init routines) [1].
[1] https://review.coreboot.org/20676
Change-Id: I699db882189f99018d4a6fdcb00f9438b2a7a1bc
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Romstage of many 440BX boards included headers that are not used.
Remove them as part of a bigger cleanup effort.
Change-Id: I89ddeda3c90e1a4907c05851185b69f3b29e54ba
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I370285aa52776170a32b6dd36c0eef74eea9400c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I1f906c8c465108017bc4d08534653233078ef32d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Do not lock ETR3 CF9GR in early romstage.
As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done
in bd82x6x's finalize handler.
Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I77aabf98ea48c6e8bdbe322f89666935f59a289a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I93f43a0af41ae86f1b8ba33e28f3b9f060a5ab5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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This board features a PATA port.
TESTED PATA drive works in SeaBIOS and OS.
Change-Id: I74dc72c22e6c4fed07f28ef7d88adde54656ae39
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.
Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Tested against a lenovo-manufactured tpm 1.2 module:
a /dev/tpm0 visible inside GNU/Linux, but there is no menu items in
SeaBIOS' interface, which seems a common issue of SeaBIOS on ivb boards.
Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/19521
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently native video init works on port HDMI1 (wired to the
on-board DVI-D socket) , HDMI3 (the on-board HDMI port), and the VGA
port, both text mode and fb mode.
Every ports works on GNU/Linux.
Tested against an IVB cpu (i7-3770T).
Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/19522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The AFC—Additional Flash Control Register is set by
southbridge code.
Remove redundant calls and get rid of it in autoport.
Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19493
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I1ef1323dc1f3005ed194ad82b75c87ef41864217
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19367
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I3a55c2e8077fdb10768df287f38efcd5e2e64bdf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19365
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This needs some extra headers in amdk8/raminit.c that were otherwise
provided by that file.
Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19360
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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For this debug.c needs to be linked too.
Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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All boards select INTEL_EDID, move it to nb folder.
Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19086
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Using linker instead of '#include *.c'.
Change-Id: I74dfa99c8bb3f4ca7ef3d774be2197897022f52c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18484
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).
Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17998
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Previously the raminit failed on hot reset and to work around this
issue it unconditionally did a cold reset.
This has the following issues:
* it's slow;
* when the OS issues a hot reset some disk drives expect their 5V
power supply to remain on, which gets cut off by a cold reset,
causing data corruption.
To fix this some steps in raminit must be ommited on the reset path.
This includes receive enable calibration.
To achieve this it stores receive enable results in RTC nvram for them
to be rewritten on the resume path.
Note: The same thing needs to be done on the S3 resume path.
Calling a hot reset after raminit "outb(0x6, 0cf9)" works.
Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18009
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This is more consistent with newer Intel targets.
This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.
Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The console output is garbled until it is fixed in ramstage
by devicetree which sets the uart clock predivider correctly.
Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17969
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
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Currently, some Intel 945 boards miss some or all of the time stamps
*1:start of rom stage*, *2:before ram initialization*, and *3:after ram
initialization*, so add them.
Use the same formatting as used for the board Lenovo X60, which already
has code for all the time stamps.
Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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If the cmos checksum is incorrect it should fall back to sane defaults.
Change-Id: If16cfc73effd4a825d0cefcd30bfd0e48b2d9132
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17968
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Correct tabs that were intended as spaces.
Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17905
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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Checking for memory self refresh can generate false positives,
as explained in faa6beb: "northbridge/intel/i945:
CHECK_SLFRCS_ON_RESUME Kconfig option".
This seems to be the case for this motherboard.
TESTED on ga-945gcm-s2l.
Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17617
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Instead of hardcoding pci_mmio_size in the raminit code,
this makes it a parameter in the devicetree.
A safe minimum of 768M is also defined since using anything
less causes problems (if 4G of ram is used).
Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16856
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17736
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17735
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ifeef04b68760522ce7f230a51f5df354e6da6607
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17734
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.
All these platforms now have MMCONF_SUPPORT_DEFAULT.
Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17529
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This mainboard is identical to ga-945gcm-s2l except for NIC
which is a Realtek RTL 8101E chip (10/100 Mbit).
The schematics of ga-945gcm-s2l mention multiple NICs and ga-945gcm-s2c
and ga-945gcm-s2l have a common manual further indicating that those
boards are close to identical.
Change-Id: Iba3d401efcf208154e639c3237b201830a5151aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17416
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Id7c2b656f500c14f39d4492667ea461b9ca353b0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17613
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ifba821a7e355a0d6689f21c7f307e3901903a3fd
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17602
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I021aae6130c475cb370b891ffaec6f1ad267540b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17580
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This motherboard support Intel core 2 quads.
Before this change SeaBIOS was not usable, due to it crashing before it
got to load anything.
Change-Id: Ifdaaceace04f9ba0753aab2d3b05c0519367f91f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17537
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Obtained from vendor bios DSDT, under "Device (HUB0),
Name (_ADR, 0x001E0000)".
The schematics also indicate that the INTA-D are hardwired to these
PIRQ lines.
Change-Id: I8e1c6cb986a2b345a5e1fddd454c7fb12fb8256a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17099
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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When MRC cache is available, first read only the SPD unique
identifier bytes required to detect possible DIMM replacement.
As this is 11 vs 256 bytes with slow SMBus operations, we save
about 70ms for every installed DIMM on normal boot path.
In the DIMM replacement case this adds some 10ms per installed DIMM
as some SPD gets read twice, but we are on slow RAM training boot path
anyways.
Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17491
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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GPIO register at offset 0xfc (VID Input Register) is read-only but
writing 1 to bit 0 will update initial VID input.
Change-Id: Ie372e98f8e497eede382975262a63d58c16227b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17412
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Startpoint was Intel d945gclf, which has same chipset and
Gigabyte ga-g41m-es2l which has same Superio.
What works and is tested:
* PCI slot;
* PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card;
* onboard VGA output (only textmode implemented) with native graphic init;
* 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset);
* serial output during and after boot.
What does not work:
* resume from suspend (does not work for d945gclf either).
Quirks:
* The Realtek ethernet card requires a reset which currently also
hardcodes a MAC adress.
This board was only tested with the SeaBIOS payload due to flash size
constraints (512KB) and with GNU/Linux.
Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17033
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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According to: "Intel ® 4 Series Chipset Family datasheet"
the IGD only has 1 IRQ pin.
Change-Id: I974f002f5a213056f4593a1eab10772527bb241d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17098
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the
gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and
vesamode in menuconfig.
Change-Id: I84b61118fa0419d49d2498b66029711cdce97576
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16501
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Id46a0c4ca59dc7224c2eedd674ea3a5486509de1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16824
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ib439e5d96543790d17934bd477af62d39a5958b6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16815
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I36011719f79da4a9ab2aaeb92ffb0506b4373143
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16816
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I038e5cea654d1760ddb2c403c651d8f75e021251
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ie752fe0a74acd4b79711596e56fc5ebf83884a0d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16779
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16730
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I341293cd334d6d465636db7e81400230d61bc693
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16723
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Idc29373cb01f4304d22ae315812bd40f0aaa94c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16729
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Replace the use of the old device_t definition inside
mainboard/gigabyte/*.
Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Although the goal was to hide the ME device by disabling
the PCI bridge, the original comment that this bridge was ME related
was a mistake, this bridge is for PEG not for ME.
We still need this PCI bridge "on" to enable pci express graphics
add-on cards.
Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16496
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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With this patch and the previous ones in this set,
PCI express graphics is now working.
01:00.0 VGA compatible controller [0300]: NVIDIA Corporation GT218
[GeForce 210] [10de:0a65] (rev a2) (prog-if 00 [VGA controller])
Change-Id: Ife691fb381e90e7744fe2ac4e20977be53419a14
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16497
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.
Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
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Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.
To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).
Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I990038c09f5805c8e670fd316808dde767e8671b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16159
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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