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2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-09Use macros to improve readability of the device-to-pin IRQ assignmentsCarl-Daniel Hailfinger
in GA-2761GXDK mptables.c. Thanks to Torsten Duwe for initial code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: 蔡明耀 (Morgan Tsai) <my_tsai@sis.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-07Improve readability and remove redundancy by wrappingTorsten Duwe
similar smp_write_intsrc calls in preprocessor macros. Also add some comments about the actual devices the INTs belong to. Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-21Add an interrupt entry for the onboard firewire controller,Torsten Duwe
Bus 1, device 10 (function 0 only), routed to IO-APIC pin 18 (verified on an v1.0 board). Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17Enable IDE legacy port access for all 440BX based boards per default, asUwe Hermann
this is needed (at the very least) to make FILO work on these boards. Disable UDMA/33 per default, which is slower but the safe choice, as we don't know which IDE devices a user has attached, and some don't support UDMA/33 very well or at all. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-22Mark devices which are not available on the board with "N/A" toUwe Hermann
make it clearer why they are disabled (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-201. Fix pirq routing table setting for GA-2761GXDK.Morgan Tsai
2. Southbridge PCIe slots are working correctly now. 3. Disable keyboard & mouse ports for GA-2761GXDK. Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14Gigabyte M57SLI: Fix watchdog clocksource to be external, not internal.Carl-Daniel Hailfinger
Reason: The existing code does not tell us why it sets the watchdog clock at all, but since it appears in cache_as_ram_auto.c instead of the usual place (Config.lb) there has to be some meaning to it. Simply do what the proprietary bios does: Use the external clock source. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14Autodetect presence of serial flash and set up the board accordingly.Carl-Daniel Hailfinger
This enables us to have only one configuration and one set of code for all revisions of the Gigabyte GA-M57SLI-S4. Flash is now setup correctly for both SPI and LPC flash. Detection of SPI flash in flashrom on rev. 2.x boards now hangs instead of failing. However, that is just an effect of the combination of incomplete initialization of the SPI controller and paranoid checks in the flashrom SPI code. If anyone wants to work on that, he needs a logic analyzer or creative imagination. Hint: LPC-to-SPI read passthrough, clock signal. Remaining issues for the M57SLI: Fan/environment control. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Harald Gutmann <harald.gutmann@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14* Maintaining SiS south bridge device IDs.Morgan Tsai
* Strip unnecessary driver modules. Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-12Fix the remaining issues with GA-M57SLI Super I/O GPIO configuration.Carl-Daniel Hailfinger
With this patch, flashing the parallel EEPROM on board revisions 1.x finally works. Flashing the serial EEPROM of board revisions 2.x is just one patch away. Torsten Duwe says: Flash erase on my board was failing reliably. Now it works! Andreas B. Mundt says: For the first time I was able to write with flashrom and LB. $flashrom -Vv --write linuxbios.rom [...] Vendor ID: GIGABYTE, part ID: m57sli Found chipset "NVIDIA MCP55", enabling flash write... OK. [...] SST49LF040B found at physical address 0xfff80000. Flash part is SST49LF040B (512 KB). LinuxBIOS last image size (not ROM size) is 4096 bytes. Manufacturer: GIGABYTE Mainboard ID: m57sli This firmware image matches this motherboard. Programming page: 0007 at address: 0x00070000 Verifying flash... VERIFIED. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Torsten Duwe <duwe@lst.de> Tested-by: Andreas B. Mundt <andi.mundt@web.de> Tested-by: Torsten Duwe <duwe@lst.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-12Try to fix a few loose ends on the GA-M57SLI Super I/O GPIO Carl-Daniel Hailfinger
configuration. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Torsten Duwe <duwe@lst.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-05Fix the M57SLI routing table, as apparently set up from LinuxBIOS onTorsten Duwe
that board. Shift PCIe pin numbers downwards, and PCI int pins upwards. This puts both PCI slots' int A and PCIe 16x int A into the right position. Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-021. vgabios removed, will go to extra repositoryMorgan Tsai
2. Rename sisnb.c to sis761.c 3. Delete many mis-definition for sis device in src/include/device/pci_ids.h 4. Trim trailing spaces for all files Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31As started in Torsten Duwe
http://www.linuxbios.org/pipermail/linuxbios/2007-October/025385.html , but change all apparantly related values that differ on my board with legacy BIOS. This makes both PCI cards appear, as well as the firewire device TSB43AB23. * PCI 01:07.0 appears fully functional * PCI 01:08.0 (closer to the board edge) appears, but no interrupts * PCI 01:0a.0 (FireWire) untested Since none of these was even present without the patch I suggest to apply it. Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Harald Gutmann <harald.gutmann@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31Add initial support for the GIGABYTE GA-6BXC.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30[LINUXBIOS] Add the CPU_OPT flag to facilitate passing flags into the buildJordan Crouse
buildROM passes build flags through the CPU_OPT environment variable - especially -fno-stack-protector for those of us lucky enough to have Debian/Ubuntu. This adds to the cache_as_ram_auto.inc target for the GA-2761GXDK so that the resulting cpu0.S is clean. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30Rename the SiS761GX/SiS966 board to the correct name, GIGABYTE GA-2761GXDK.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-22reverting 2683, NAK by YhLu, patch not necessary.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21The Gigabyte m57sli-s4 board supports Rev. F CPUs.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-26Activate EC for access to fan speeds and temperature sensors.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06Disable USB console on the m57sli for now.Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-27This is another fixup round for Yinghai Lu's great patch.Stefan Reinauer
It does the ROM_STREAM -> PAYLOAD rename that afaik was done after Yinghai sent his work to legal, so it is required to get that code building. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-19Fix some CHIP_NAME() entries to use canonical names.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-17Initial support for the following new mainboards:Yinghai Lu
* Nvidia l1_2pvv * Gigabyte m57sli * Supermicro h8dmr * Tyan s2912 -- with HTX The boards will currently _not_ compile, two further patches from Yinghai Lu are still missing. Please be patient :) Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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