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2017-10-22superio/ite/common: Add temperature offsetVagiz Trakhanov
Add a devicetree option to set temperature adjustment registers required for thermal diode sensors and PECI. However, this commit does not have the code needed to make PECI interface actually use these registers. It only applies to diodes. As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3". PECI, apparently, takes precedence over diode, so the adjustment register will be set and PECI activated. Or simply use the followup patch, which makes THERMAL_PECI a mode like THERMAL_DIODE. I don't have hardware to test THERMAL_DIODE mode, but in case of PECI, without this patch I had about -60°C on idle. Now, with offset 97, which was taken from vendor bios, PECI readings became reasonable 35°C. TEST=Set a temperature offset, then ensure that the value you set is reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-12mb/foxconn/g41s-k: add new mainboardSamuel Holland
Based on the Intel G41 chipset, ICH7 southbridge, and IT8720F Super I/O. Tested, working: * Booting Linux 4.11.3 and Windows 8.1 from USB and HDD * Resume from S3 (Linux and Windows) * Native raminit (DDR2-800) * Native graphics init (SeaBIOS, Linux) * Graphics init with VGA BIOS (SeaBIOS, Windows) * PCI-E x16 PEG slot, PCI-E x1 slot from southbridge * Realtek ALC888 HD Audio (including front panel and jack detection) * Realtek R8168 Gigabit LAN * Both SATA ports * USB 1.1 and 2.0 devices (keyboard, mass storage) * PC speaker beep * COM header * Super I/O Environment controller (temps, voltage, fans) * PS/2 keyboard and mouse * Flashing with `flashrom -p internal` * 1MiB and 2MiB SPI flash chips * CMOS gfx_uma_size Appears, OS driver loads, but otherwise untested: * IrDA header * CIR header * TPM header Untested: * S/PDIF digital audio Tested, known broken: * CMOS power_on_after_fail * USB keyboard in secondary payloads Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20027 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>