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2021-01-10soc/intel: Replace acpi_init_gnvs()Kyösti Mälkki
Rename these to soc_fill_gnvs() and move the callsite away from mb/. Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/x/acpi_tables: Rename to mainboard_fill_gnvs()Kyösti Mälkki
Rename acpi_create_gnvs() functions under mb/ to reflect their changed functionality. Remove now empty mb/acpi_tables.c files. Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/braswell: Clean up devicetree settingsAngel Pons
Remove unreferenced settings and factor out common settings. Many of these are not mainboard-specific, and all boards use the same value. Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03cbfstool: Use cbfs_serialized.h and standard vboot helpersJulius Werner
This patch reduces some code duplication in cbfstool by switching it to use the CBFS data structure definitions in commonlib rather than its own private copy. In addition, replace a few custom helpers related to hash algorithms with the official vboot APIs of the same purpose. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I22eae1bcd76d85fff17749617cfe4f1de55603f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-11-23mb/**/cmos.layout: Indent everything with tabsAngel Pons
Time has shown that using spaces never converges into proper alignment. Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-23mb/**/cmos.layout: Remove crusty commentsAngel Pons
Most of these comments have been copy-pasted or serve no purpose other than to eventually turn into misleading info. While the description of the first 120 bits of CMOS could be useful, it should instead be added to the documentation for the CMOS option infrastructure, or /dev/null. Moreover, trim down newlines to no more than two consecutive newlines. Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-22mb/facebook/fbg1701/Kconfig: Add dependencyFrans Hendriks
VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled. Add dependency of USE_VENDORCODE_ELTAN. Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22mb/facebook/fbg1701: Add VBOOT supportFrans Hendriks
Add VBOOT support. Disable USE_VENDOR_ELTAN when VBOOT is enabled. Add FMD file and split binary into RW and RO region settings. Tested on Facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-11-13soc/intel/{skl,cnl}: replace PM ACPI timer dt option by KconfigMichael Niewöhner
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-16soc/intel/skylake: Rename PcieRpAspm devicetree configBenjamin Doron
This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-12mb/facebook: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I91f65fecdcdf41dc41f136e8d66bbf730343aef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46078 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-08soc/intel/skylake: Enable CIO depending on devicetree configurationFelix Singer
Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08soc/intel/skylake: Enable SA IMGU depending on devicetree configurationFelix Singer
Currently, SA IMGU gets enabled by the option SaImguEnable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SA IMGU controller. All corresponding mainboards were checked if the devicetree configuration matches the SaImguEnable setting, and missing entries were added. Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-07soc/intel/skylake: Enable thermal subsystem depending on devicetreeFelix Singer
Currently SA thermal subsystem gets enabled by the option Device4Enable, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the SA thermal subsystem controller. All corresponding mainboards were checked if the devicetree configuration matches the Device4Enable setting, and missing entries were added. Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable HDA depending on devicetree configurationFelix Singer
Currently HDA gets enabled by the option EnableAzalia, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HDA controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableAzalia setting. Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable eMMC depending on devicetree configurationFelix Singer
Currently eMMC gets enabled by the option ScsEmmcEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the eMMC controller. I checked all corresponding mainboards if the devicetree configuration matches the ScsEmmcEnabled setting. Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-29soc/intel/skylake: Enable SMBus depending on devicetree configurationFelix Singer
Currently SMBus gets enabled by the option SmbusEnable, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SMBus controller. I checked all corresponding mainboards if the devicetree configuration matches the SmbusEnable setting. Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-29soc/intel/skylake: Enable LAN depending on devicetree configurationFelix Singer
Currently LAN gets enabled by the option EnableLan, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableLan setting. Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-29soc/intel/skylake: Enable SATA depending on devicetree configurationFelix Singer
Currently SATA gets enabled by the option EnableSata, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SATA controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableSata setting. Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-26skylake boards: Factor out copy-pasted PIRQ routesAngel Pons
Put them in common code just in case something depends on the values. Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-07acpi: Rename motherboard_fill_fadt() to mainboard_fill_fadt()Kyösti Mälkki
The prefix mainboard_ was used everywhere else. Change-Id: Ie576fd47301aa484cb1396e0c6f7260b7698af4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-07soc/intel/baytrail,braswell,broadwell,quark: Select COMMON_FADTKyösti Mälkki
Some of the boards do not select SYSTEM_TYPE_LAPTOP or _CONVERTIBLE so their FADT preffered_pm_profile would change from PM_MOBILE without the added overrides here. Change-Id: I04b602b2c23fbd163fcd110a44ad25c6be07ab66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41920 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07mb,soc/intel: Rename acpi_fill_in_fadt() to acpi_fill_fadt()Kyösti Mälkki
Change-Id: I9025ca3b6b438e5f9a790076fc84460342362fc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41919 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07acpi,mb/*: Use motherboard_fill_fadt()Kyösti Mälkki
By vendor choice override fadt->preferred_pm_profile here. Change-Id: I0453c0edc9aeb86cf4f5d912613b8fa8beb63ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41917 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cbfs.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cbfs.h>' -- src/) <(git grep -l 'cbfs_boot_map_optionrom\|cbfs_boot_map_optionrom_revision\|cbfs_boot_locate\|cbfs_boot_map_with_leak\|cbfs_locate_file_in_region\|cbfs_boot_load_file\|cbfs_load_and_decompress\|cbfs_prog_stage_load\|cbfs_boot_region_device' -- src/) |grep '<' |grep -v vendorcode Also add missing 'include <cbfs.h>' in src/soc/qualcomm/sc7180/qupv3_config.c Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/facebook/fbg1701: Remove C_ENV_BOOTBLOCK_SIZEKyösti Mälkki
Remove the use of C_ENV_BOOTBLOCK_SIZE. Verify the bootblock by reading the CBFS file instead of directly accessing the datablock. BUG=None BRANCH=None TEST=tested on facebook fbg1701 Change-Id: I4254d681525327c7eec18832586818e9c4e8eb22 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41694 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove unused 'include <lib.h>'Elyes HAOUAS
Change-Id: Iad5540e791075270453a136a058823c28647f93a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18mb/facebook/fbg1701: Remove direct 'include <soc/gpio.h>'Elyes HAOUAS
Don't directly include <soc/gpio.h>. All code using GPIO features should always and only include <gpio.h>, which should indirectly include the SoC-specific <soc/gpio.h>. Change-Id: Id2663398b9f069ab1f60d63016ea7aa080f66d20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18mb/facebookmonolith: Update root port settingsWim Vervoorn
Update monolith root port settings to match those of the original BIOS. MaxPayload is set to 256 bytes, ASPM is disabled and LTR and Advanced Error reporting are enabled. BUG=N/A TEST=tested on facebook monolith Change-Id: Idf6e706d45cf1ea1aee4a75a6d0eb130b21db927 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-05-18mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08mainboard/*/*.spd.hex: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I3eb39d985f2712ab0a7a5a76b06ed625eb51c9d0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41140 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-14mb/facebook/monolith: Add fmd files for 6MB BIOS areaWim Vervoorn
The current flash layout requires changes to the descriptor area to create the 9MB BIOS region. Add fmd files that allow switching to coreboot by only replacing the BIOS region. BUG=N/A TEST=tested on facebook monolith Change-Id: I2b003018e245693934202505d7e3891c2f545e6c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-04-04mainboard/facebook: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I311c62e8321afa43fdb442e10158973ecdcca793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-26mb/facebook/monolith: Update GT-Sliced icc_maxWim Vervoorn
Update the icc_max for the GT-Sliced VR domain according to the hardware design. BUG=N/A TEST=build Change-Id: Ib9f7d77d144a282214e6bda8a4e836873c395487 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39804 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25mb/facebook/monolith: Configure COMB to 0x3e8Wim Vervoorn
The 2nd COM port's base address defaults to 0x2f8. Current software for this system expects the port at 0x3e8. Configure COMB to use 0x3e8 instead of 0x2f8. BUG=N/A TEST=tested on facebook monolith Change-Id: Ibb462bad5f0594e0b5c8dea6e02cd42d58d999ab Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18mainboard/[a-f]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-03-03mb/*/Kconfig: Factor out MAINBOARD_VENDORAngel Pons
Only some mainboard vendors have a prompt for this option. Let's be fair and give this ability to everyone. Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-18mb/facebook/monolith: Use serial number and UUID from VPDWim Vervoorn
The serial number and UUID returned by DMI are retrieved from VPD. The solution supports a 16 character "serial_number" and a 36 character "UUID" string. BUG=N/A TEST=tested on monolith Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-18mb/facebook/monolith: Enable use of VPDWim Vervoorn
Enable use of VPD for monolith. This will be used to store the UUID and Serial number. BUG=N/A TEST=build Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-11mb/facebook/monolith: Enable the 2nd EC UART at 0x2f8Wim Vervoorn
BUG=N/A TEST=tested on facebook monolith Change-Id: I36e652e66c66eeb770a5a5d987bb57c7eaa11382 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38749 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22mb/facebook/fbg1701: Remove ACPI S4 supportWim Vervoorn
Align the fbg1701 sleepstates implementation with monolith. BUG=N/A TEST=build Change-Id: I3a715781bf51da41d6954463ad38ed94b0dfd217 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-22mb/facebook/monolith: Disable S3 and S4Wim Vervoorn
The monolith board doesn't support the S3 and S4 states because of the watchdog and failover mechanisms. Remove S3 and S4 from the available sleepstates. BUG=N/A TEST=build Change-Id: I01f67d8bb3f9e45caef748caca91eeb6859d7393 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-20mb/facebook/monolith: Drop PWRB deviceWim Vervoorn
The mainboard ASL code contained a power button definition. This is not required as the system uses the standard ACPI power button. Remove the PWRB device from ASL. BUG=N/A TEST=tested using fwts on a facebook monolith. Found-by: fwts 19.12.00 Change-Id: I25a842539ee2e8febc8a1ae88843a71ccb4ee68e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38133 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20{mb/facebook/fbg1701,mb/portwell/m107}: Drop PWRB deviceWim Vervoorn
The mainboard ASL code contained a power button definition. This is not required as the system uses the standard ACPI power button. Remove the PWRB device from ASL. BUG=N/A TEST=build Found-by: fwts 19.12.00 Change-Id: I4fac1411fd99475551bc970818759649f80b3f0e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38134 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/facebook/monolith: Enable the xDCI controllerWim Vervoorn
Enable the VBOOT_ALWAYS_ALLOW_UDC option to actually enable the xDCI controller. BUG=N/A TEST=build Change-Id: Ib51f2c82e69db83cebceb71ba5f1305764e0feca Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mb/facebook/monolith: Describe device 4.0 in devicetreeWim Vervoorn
BUG=N/A TEST=build Change-Id: Id7267aa6d4266bb7807fb3c25b5e2704c8d81df7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38430 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/facebook/monolith: Add support to read cpu temperatureWim Vervoorn
Read the CPU temperature from the EC. For this board the EC support is limited to reading the CPU temperature sensor at this moment. Events are not supported. BUG=N/A TEST=tested on facebook monolith using acpidbg The TSR0._TMP method is returning the correct values. Change-Id: I6793070602e253f1e15cfc641bb47d25d269b136 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mb/facebook/monolith: Update power supply settingsWim Vervoorn
Update the IccMax for the SYSTEM_AGENT and IA_CORE power supplies according to the information in the schematic. The IccMax for these supplies is lower than the standard supported by the SoC. BUG=N/A TEST=build Change-Id: I20b92e7dfc85427bcf9cb9f0efda02459c862809 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-13mb/facebook/monolith: Enable SpeedStep and DPTFWim Vervoorn
BUG=N/A TEST=tested using fwts on facebook monolith. Change-Id: Ia3dd195f887055448d42a7584e2c88322f0ec44b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10src: Remove blank acpi_tables source filesKarthikeyan Ramasubramanian
Due to build rules, dummy acpi_tables source files were added in many mainboards. With commit 1e83e5c61a3aa98f58f7d8cbf8d1eb9532896cc3 ("src/arch/x86: Build mainboard acpi_tables source if present"), the build system will build mainboard acpi_tables only if present. Remove the dummy/empty/blank acpi_tables source files. BUG=None TEST=Build test with some google mainboards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0cef34368e2e5f5e3b946b22658ca10c7caad90a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-10mb/facebook/monolith: Remove SDIO controller from devicetreeWim Vervoorn
The SDIO device is disabled so remove it from the devicetree. BUG=N/A TEST=build Change-Id: I6497f6134d8fc001bf4cb7e348ae00077aa34814 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38129 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/facebook/monolith: Enable HDA for HDMI outputWim Vervoorn
The HDA controller was disabled because no codec exists on the board. However, this also disabled audio over HDMI. To correct this, enable Azalia and the HDA controller in the devicetree. BUG=N/A TEST=tested on facebook monolith Change-Id: I7be2c29151dc9d6c247c3332fb9adfb34449c703 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10mb/facebook/monolith: Add UNIFIED_MRC_CACHE region in fmd fileWim Vervoorn
The RW_MRC_CACHE was not included in a UNIFIED_MRC_CACHE region which is expected by some parts of the code. Add the UNIFIED_MRC_CACHE and include the RW_MRC_CACHE in this region. BUG=N/A TEST=tested on facebook monolith Change-Id: I1654ca210dc2a8e976d698fd8330641da23e8380 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/**/devicetree.cb: Remove untrue commentsAngel Pons
Even if they were corrected, they just rephrase the code. Change-Id: Iebc4e8c9eb0f44f84acf532ad12a5d064075a102 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-02mb/**/hda_verb.{c,h}: use denary numerals for codec IDsAngel Pons
Denary, also known as "decimal" or "base 10," is the standard number system used around the world. Therefore, make use of it. Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-12-31mb/**/dsdt.asl: Remove outdated sleepstates.asl commentAngel Pons
Previously, each Intel chipset had its own sleepstates.asl file. However, this is no longer the case, so drop these comments. Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-21mb/**/dsdt.asl: Remove "Some generic macros" commentAngel Pons
It provides no useful information, so it might as well vanish. Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-20mb/facebook/fbg1701: Correct typo in hda verbsWim Vervoorn
The MIC1 NID is configured incorrectly because of a typo. The value is 7 digits instead of 8. This is corrected by this patch. No issues are known because of this (the MIC is not connected). BUG=N/A TEST=build Change-Id: Ia12f3be7d7262829cce3400a8535a33ea1c54b78 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-16mb: Use fixed value in RcompTarget structureWim Vervoorn
Now RCOMP_TARGET_PARAMS is defined and used once in the definition of the RcompTarget structure. All other structures in these functions use a fixed value. Replace RCOMP_TARGET_PARAMS with fixed value. BUG=N/A TEST=build Change-Id: Ibe7c72c65975354433e9a0c613bda715eb782412 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37658 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16mb/facebook/monolith: Add vboot-ro.fmd to support measured bootWim Vervoorn
Add an fmd file with a layout that allows configuring the system for measured boot without enabling verified boot. BUG=N/A TEST=tested on facebook monolith Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37673 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16mb/facebook/monolith: Remove % tag from fmd fileWim Vervoorn
cbfstool doesn't support % tag yet while this was in the fmd. Revert the fmd changes that use the % tag. BUG=N/A TEST=build Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16mb/facebook/monolith/gpio.h: Update GPIO configurationWim Vervoorn
Update signal names and GPIO configuration. Remove unused GPE_EC_WAKE and EC_XXX_GPI defines. BUG=N/A TEST=tested on facebook monolith Change-Id: Iae5edb8418894a669ed49c2d78672d8957010f3c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11mb/{facebook/portwell}: Remove empty onboard.hFrans Hendriks
Defines in onboard.h are moved to other files. Remove this empty and unused file. BUG=N/A TEST=build Change-Id: Ide10b352eadcffad2d4221865124f64466af5a1c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37615 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11mb/facebook/fbg1701: Move verified items to board_verified_boot.hFrans Hendriks
Items in onboard.h are related to verified or measured boot. Move the items to board_verified_boot.h and remove onboard.h. BUG=N/A TEST=build Change-Id: Icfc8d6d8351f0654c277e81c7f3cc2b0a947866a Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37614 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11mb/{facebook/portwell}: Define SDCARD_CD in dsdt.aslFrans Hendriks
SDCARD_CD is defined in onboard.h but required in ASL only, move this define to dsdt.asl. Removed the onboard.h file from the ASL files that don use it. BUG=N/A TEST=build Change-Id: I35b75e0ae2e2bc4ce143aaec6df6016774676095 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11mb/facebook/fbg1701/acpi/ec.asl: Remove headerFrans Hendriks
File contains header only. Remove header leaving an empty file. BUG=N/A TEST=build Change-Id: I8b1c6b38bd7936cc7af11c13744325bed23a6e83 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-10mb/{facebook/portwell}: Remove ITE8258_CMD_PORTFrans Hendriks
ITE8258_CMD_PORT is used in com_init.c only. Replace ITE8258_CMD_PORT by fixed value in the c file. ITE8258_DATA_PORT is removed as this isn't used. BUG=N/A TEST=build Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-06mb/facebook/monolith: Add Facebook MonolithWim Vervoorn
The board is booting Linux and has been briefly tested. SeaBIOS, TianoCore payload and Linux as payload all seem to work fine. BUG=N/A TEST=tested on Facebook Monolith Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-05soc/intel/braswell: Use common sb code for SPI lockdown configurationArthur Heymans
This removes the weakly linked function to configure the SPI lockdown. Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25Drop superfluous C_ENVIRONMENT_BOOTBLOCK checksArthur Heymans
Some guarding is not needed because the linker drops the code, other guarding is not needed because all platforms using the code now have C_ENVIRONMENT_BOOTBLOCK. Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-21mb/*/*: Remove BROADWELL_DE boardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-15mb/facebook/fbg1701: Select HAVE_IFD_BIN and HAVE_ME_BINFrans Hendriks
Add IFD and ME binary to generate complete SPI image. BUG=N/A TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701 Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34448 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15mb/facebook/fbg1701: Remove logo from verify list when disabledWim Vervoorn
Remove the logo.bmp file from the verify list when FSP1_1_DISPLAY_LOGO is not set. BUG=N/A TEST=build Change-Id: I87eac0b3cbe9450d5623b5331d8de096f140b595 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36853 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15mb/facebook/fbg1701: Changed the order of the verify_listsWim Vervoorn
Changed the order of the verify lists and updated the comments to reflect the order of execution. This makes the list easier to understand and maintain. BUG=N/A TEST=tested on fbg1701 Change-Id: Ia656fbf07e5d42bafd328eaba69b660e5a1e4f1a Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36817 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15mb/facebook/fbg1701: Stagenames now use CONFIG_CBFS_PREFIXWim Vervoorn
Change from hardcoded "fallback/*" to using CONFIG_CBFS_PREFIX. BUG=N/A TEST=tested on fbg1701 Change-Id: Ie728d01ebb93edd88516e91528ecaaa3f139b7a9 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-15mb/facebook/fbg1701: Only verify the publickey when neededWim Vervoorn
The public key should only be validated if the manifest is signed. BUG=N/A TEST=testedd on fbg1701 Change-Id: I703ed442e0b1926859f593ce9ca84133013224ea Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-15mb/facebook/fbg1701: Removed unused include fileWim Vervoorn
Removed unused include file. BUG=N/A TEST=build Change-Id: I040b695a893b51de06f9658abdca8867727f053d Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-15mb/facebook/fbg1701: Correct the postcar_verify_listWim Vervoorn
The postcar_verify_list should contain the items that should be verified before the postcar stage is started. BUG=N/A TEST=build Change-Id: I328858e4803873fed6d47313def5e7b9a434e8ad Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-15mb/facebook/fbg1701: Align handling of bootblock and publickeyWim Vervoorn
The bootblock measurement was handled using the romstage_verify_list() and the public_key in the mb_log_list. This is confusing as these are both read-only items that should be handled in the same way. Both will be handled in the romstage_verify_list(). BUG=N/A TEST=tested on fbg1701 Change-Id: If05198deec85188f39a221a8b755798755afa5bb Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-14{drivers,mainboard}: Move FSP logo support to fsp1_1Frans Hendriks
Support to display a logo using FSP 1.1 currently resides in facebook fbg1701 mainboard. The related support is moved to drivers/intel/fsp1_1 and used by the Facebook fbg1701 mainboard. The storage for the uncompressed logo is changed. We don't use .bss any longer as the logo doesn't need to be available at runtime. BUG=N/A TEST=booting Facebook fbg1701 Change-Id: I276e6e14fc87d0b95fe5fdf7b617afd26769de79 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-10drivers/intel/fsp1_1: Fake microcode update to make FSP happyArthur Heymans
The FSP loops through microcode updates and at the end checks if the microcode revision is not zero. Since we update the microcode before loading FSP, this is the case and a fake microcode can be passed to the FSP. The advantage is that the Kconfig symbols to specify the location and the size of the microcode blob can be dropped. Change-Id: I63cfb7b19e9795da85566733fb4c1ff989e85d03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36255 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-08mb/facebook/fbg1701: Remove some preprocessor guardsKyösti Mälkki
Change-Id: Ia7289fa8337e1a93e620a52a67ca8cbdd78a66bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-05vendorcode/eltan/security: Align mboot with coreboot tpmWim Vervoorn
Align the eltan mboot support with coreboot tpm support to limit the amount of custom code. We now only support SHA256 pcrs, only single a single digest will be handled in a call. The pcr invalidation has been changed fixed values are now loaded while the correct algortihm is selected. BUG=N/A TEST=tested on fbg1701 Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-04mb/facebook/fbg1701: Add logo to the menuWim Vervoorn
Allow the user to enable and disable the logo from make menuconfig. The file can be selected as well. BUG=N/A TEST=build Change-Id: I630a9d14308131c180adaaa9e1fa5e6e11c3c61c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 03:22:43 +0000