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path: root/src/mainboard/esd/atom15/Kconfig
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2019-11-21mb/*/*: Drop FSP_BAYTRAIL supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-08intel/fsp_baytrail: Move TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: Ib61ea29724401146eb6f008374cdf599f418e81f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-31cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDENico Huber
As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-13FSP1_0 does not support HAVE_ACPI_RESUMEKyösti Mälkki
FSP1_0 places romstage ram stack at fixed location of RAMTOP in low memory before returning to coreboot proper. There is no possibility of making a complete backup of RAMBASE..RAMTOP region and currently such backup is not even attempted. As a conclusion, S3 resume would always cause OS memory corruption. Change-Id: I5b9dd4069082e022b01b0d6a9ad5dec28a06e8b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-04esd/atom15: import esd atom15 boardMichael Tasche
This patch adds esd atom15 board with Intel Atom E3815 SoC. Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12632 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>