| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-08-02 | arch/riscv: Add include/arch/barrier.h | Jonathan Neuschäfer |
| 2016-07-14 | spike-riscv: Look for the CBFS in RAM | Jonathan Neuschäfer |
| 2016-07-14 | spike-riscv: Register RAM resource at 0x80000000 | Jonathan Neuschäfer |
| 2016-07-12 | spike-riscv: Remove HTIF related code | Jonathan Neuschäfer |
| 2016-06-21 | riscv-spike: Move coreboot to 0x80000000 (2GiB) | Jonathan Neuschäfer |
| 2016-06-17 | Define RAMTOP for x86 only | Kyösti Mälkki |
| 2016-06-12 | riscv-spike: Replace custom UART with a memory-mapped 8250 | Jonathan Neuschäfer |
| 2016-04-28 | Add board URLs for the RISC-V boards | Jonathan Neuschäfer |
| 2016-04-28 | Fix "Spike RISCV" board name | Jonathan Neuschäfer |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-09-16 | riscv-memlayout: fix existing memlayout issues, add sbi interface | Thaminda Edirisooriya |
| 2015-09-10 | riscv-trap-handling: Add implementation for trap calls in riscv | Thaminda Edirisooriya |
| 2015-08-09 | riscv-spike: support for Spike emulation of riscv | Thaminda Edirisooriya |
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index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |