coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2016-10-15	riscv: Use the generic src/lib/bootblock.c	Jonathan Neuschäfer
	TEST=Compiled for and ran on spike; it booted as before. Change-Id: Id173643a3571962406f9191db248b206235dca35 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16995 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-14	spike-riscv: Look for the CBFS in RAM	Jonathan Neuschäfer
	Change-Id: I98927a70adc45d9aca916bd985932b94287921de Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15285 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-08-09	riscv-spike: support for Spike emulation of riscv	Thaminda Edirisooriya
	Spike support: QEMU RISCV is broken, and the maintainers at Berkeley are working on it, but at the moment spike is the only way to test on riscv. Add support for spike console output for debugging. Privileged ISA: Update to privileged ISA in RISCV (machine, supervisor, hypervisor, user modes) broke exisitng RISCV asm, and bootblock.S was updated to match the new spec. Clean old assembly [pg: things build with gcc 4.9 now, but don't expect them to work. Hardcoding register names into the assembler language may not be the smartest idea of the RISCV folks.] Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>