coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	src/: Replace GPL boilerplate with SPDX header	Patrick Georgi
2020-03-18	mainboard/[a-f]*: Remove copyright notices	Patrick Georgi
2019-12-06	mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.	Philipp Hug
2018-12-05	mb/emulation/spike-riscv: Implement mtime_init	Jonathan Neuschäfer
2016-11-07	riscv: Unify SBI call implementations under arch/riscv/	Jonathan Neuschäfer
2016-10-15	riscv: Use the generic src/lib/bootblock.c	Jonathan Neuschäfer
2016-07-14	spike-riscv: Look for the CBFS in RAM	Jonathan Neuschäfer
2015-08-09	riscv-spike: support for Spike emulation of riscv	Thaminda Edirisooriya