| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-04-06 | New mechanism to define SRAM/memory map with automatic bounds checking | Julius Werner |
| 2015-03-20 | bootblocks: use run_romstage() | Aaron Durbin |
| 2015-03-20 | romstages: use common run_ramstage() | Aaron Durbin |
| 2014-12-04 | RISCV: get RISCV to build again | Ronald G. Minnich |
| 2014-12-01 | Add UCB RISCV support for architecture, soc, and emulation mainboard.. | Ronald G. Minnich |
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index : coreboot.git | |
| my copy of coreboot | User & |
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