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path: root/src/mainboard/emulation/qemu-aarch64
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2020-12-02cbfs: Enable CBFS mcache on most chipsetsJulius Werner
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-04mb/emulation/qemu-aarch64: Add a timestamp regionArthur Heymans
The romstage region is moved up a bit more to satisfy the MMU. Change-Id: I00c2b4972495fa669d4dc2a52f298a0e4d0cf5ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-12include/console/uart: make index parameter unsignedFelix Held
The UART index is never negative, so make it unsigned and drop the checks for the index to be non-negative. Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-01mb/*/Kconfig: Drop redundant 'select CONSOLE_SERIAL'Elyes HAOUAS
'CONSOLE_SERIAL' is already set to 'y' at src/console/Kconfig. Change-Id: I350cf12a115c6ebe54a2b0821edc94c29db8d137 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-26src: Remove unused 'include <cbmem.h>'Elyes HAOUAS
Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/emulation/qemu-aarch64: Fix up license headerAngel Pons
Change-Id: I9730680a8359407a2a03dbb7243a6547420e1f39 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43856 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/emulation: Remove fake devicetree.cb componentsKyösti Mälkki
Change-Id: I31853e3ede786eb9e10704674e42dd56c3a48688 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2020-05-18mainboard/*/*/*.cb: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-18mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10src/mb: Remove unneeded spaces before/after tabsElyes HAOUAS
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-04mainboard/emulation: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I68d2a8ac6f201f3c1131252b2b53b2b17ece1db6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18mainboard/[a-f]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-03-02mb/emulation/qemu-aarch64: Add ARM trusted firmware supportPatrick Rudolph
Linux expects a working PSCI and hangs if not found. Add BL31 into CBFS as '-M virt,secure=on -bios ' commands line arguments cause qemu's internal PSCI emulation to shutdown. BL31 is placed in qemu's SECURERAM memory region and won't conflict with resources in DRAM. Tested on qemu-system-aarch64: Fixes a hang and allows to boot into Linux 5.4.14 userspace. Change-Id: I809742522240185431621cc4fd8b9c7deaf2bb54 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02mb/emulation/qemu-aarch64: Add MMU supportPatrick Rudolph
Enable MMU in bootblock. Makes qemu look more similar to real hardware. There's no real need to activate the MMU. Tested on qemu-system-aarch64: 5 page entries are used out of 32. Change-Id: Ifaed9d3cc11520f180a732d51adce634621b5844 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38534 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11fmap: Make FMAP_CACHE mandatory if it is configured inJulius Werner
Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the pre-RAM FMAP cache code, there's no point in allowing the region to be optional anymore. This patch makes the section required by the linker. If a board doesn't want to provide it, it has to select NO_FMAP_CACHE. Adding FMAP_CACHE regions to a couple more targets that I think can use them but I don't know anything about... please yell if one of these is a bad idea and I should mark them NO_FMAP_CACHE instead. Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-03arch/arm64: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Currently the old infrastructure to pass on information from romstage to ramstage is left in place and will be removed in a follow-up commit. Nvidia Tegra will be handled in a separate patch because it has a custom ramstage entry. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be replaced in a followup commit. Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-01lib/cbmem_top: Add a common cbmem_top implementationArthur Heymans
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26mainboard/emulation/qemu-aarch64: Update DRAM_SIZE_MBAsami Doi
DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M) that’s possible with QEMU on AArch64 virt because it tries to search the DRAM_SIZE_MB range to find the true memory size. Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/35024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-08mainboard/emulation/qemu-aarch64: Add new board for ARMv8Asami Doi
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu via a flag. To execute: $ qemu-system-aarch64 -M virt,secure=on,virtualization=on \ -cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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