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Looking at Intel document 759603 revision 001, Alder Lake N only has 5
PCIe clock outputs and clock request pins. I only have the version 2 of
this board which has a significantly different USB port configuration to
version 1, but there the Ethernet controller on RP 11 and the E key m.2
slot on RP 12 share the last PCIe clock output. The on-board TUBF0304
clock buffer chip takes the clock output form the last PCH PCIe clock
generator output and drives the clock inputs of both the last Ethernet
chip and the E key m.2 slot. Since the last clock output is always
active, since RP 11 has the PCIE_RP_CLK_REQ_UNUSED flag set, using the
non-existent clock output and request for RP 12 didn't break things.
ASPM L0s might still work though, since that one doesn't involve
switching off the PCIe reference clock, but haven't tested that yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I103f7c3fe0b806f5c0a5202b8221f522a4b1c378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83911
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on
the mainboard and likely also routes one USB2 port to the m.2 E key slot
which is typically used for Bluetooth support when an E key m.2 WIFI +
Bluetooth card is installed.
This is untested, since I only have the cw-al-4l-v2.0 mainboard, but
from looking at the documentation of the version 1 and looking at how
things are done on the version 2 this should be correct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83910
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Currently, the 3rdparty/fsp submodule contains only the IoT FSP for
ADL-N. However, coreboot's Kconfig is incorrectly applying the IoT
FSP for both Client and IoT configurations, despite the Client FSP
requiring distinct headers.
The CWWK CW-ADL-4L-V1.0 board relies on the FSP provided by the
3rdparty/fsp submodule, which means it has been using the IoT FSP by
default. To ensure the board continues to use the correct FSP as we
plan to introduce Client FSP headers into vendorcode, we are now
explicitly select FSP_TYPE_IOT for the CWWK CW-ADL-4L-V1.0 board.
Change-Id: Ie3844cb24740e4d95ee835a44e55b4d5cb6854e5
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82915
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Brandon Weeks <bweeks@google.com>
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This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE
ports, similar boards are available in other port configurations. As a
low cost, relatively high performance board with 4 NICs, it is well
suited for networking or 'homelab' tasks.
CPU: Intel N100 or N350
Memory: DDR5-4800 SODIMM (max 16 GB)
NIC: 4x Intel I226-V 2.5 GbE
Expansion:
- M.2 2230 E key
- M.2 2280 M key
- USB 2.0 header
- Fan header
External ports:
- DC power
- 4x Ethernet
- Display Port
- HDMI
- 4x USB 2.0
- Micro SD
Working:
- Boots Debian 12 with SeaBIOS and EDK II payloads
- Serial port
- External USB ports
- DisplayPort / HDMI
- 4x Intel I226 2.5 GbE NICs
- M.2 ports
- Micro SD slot
- ACPI S3
Not working / not tested:
- Fan (ITE IT8613E)
- Audio
- S0ix
- Internal USB ports
VBT extracted from vendor UEFI firmware version ADLN 0.01 x64
(04/04/2023 11:42:38).
Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be
Signed-off-by: Brandon Weeks <me@brandonweeks.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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