coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2016-10-07	src/mainboard: Remove whitespace after sizeof	Elyes HAOUAS
	Change-Id: Ie2a047d35e69182812c349daedc5b3b5fde20122 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16860 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-26	mainboard///mptable.c: Improve code formatting	Elyes HAOUAS
	Change-Id: I341293cd334d6d465636db7e81400230d61bc693 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-23	src/mainboard: Remove unnecessary whitespace before "\n"	Elyes HAOUAS
	Change-Id: I9789b0b3339435fbe30c69221826bf23c9b3c77b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16283 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-17	mainboard: Clean up boot_option/reboot_bits in cmos.layout	Nico Huber
	Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-14	src/mainboard: Capitalize ROM, RAM, CPU and APIC	Elyes HAOUAS
	Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-30	mainboard/bap/ode_e21XX: Add board support	Fabian Kunkel
	Add next generation of BAPs (https://www.unibap.com/) SOC module, called ode_e21XX. Hardware is similar to e20XX (AMD G-Series GX-411GA Kabini), but it includes a new AMD G-Series GX-412HC (Steppe Eagle) and an updated Microsemi FPGA. Changes to Olivehillplus: - Add SuperIO Fintek F81866D - Soldered down DDR3 with ECC - User can choose between different DDR3 clk settings (lowest setting can save up to 1.2W) - Soldered down Microsemi M2S060 FPGA on PCIe lanes 2-3 Tested with: - Payload SeaBIOS 1.9.1 - Lubuntu 16.04, Kernel 4.4.0 - Windows 10 (UART functionality) Known problems: - S3 not working - IOMMU not working Change-Id: I41f6a3334ad2128695a3f7c0a6444f1678d2626e Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15918 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30	mainboard/bap/ode_e21XX: Add copy of amd/olivehillplus	Fabian Kunkel
	Initial copy of olivehillplus. Change-Id: Ibe9b450c05bfad15a95852addb1465ac2d3cef61 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15917 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>