| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-12-05 | nb/intel/x4x: Remove apic 0 from devicetree | Arthur Heymans |
| 2022-12-05 | cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm | Arthur Heymans |
| 2022-12-01 | nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree | Arthur Heymans |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-05-10 | src/mainboard: Replace GPLv2 long form headers with SPDX header | Elyes HAOUAS |
| 2020-01-10 | mb/asus/p5ql-em/devicetree.cb: Do minor fixes | Angel Pons |
| 2019-11-12 | sb/intel/i82801jx: Add common code for LPC decode | Arthur Heymans |
| 2019-11-11 | mb/asus/p5ql-em: Fix S3 resume | Arthur Heymans |
| 2019-11-09 | mb/asus/p5ql-em: Add mainboard | Arthur Heymans |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |